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latticeecp2/m family data sheet ds1006 version 02.7, july 2007
www.latticesemi.com 1-1 ds1006 introduction_01.5 july 2007 advance data sheet ds1006 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. features high logic density for system integration 6k to 95k luts 90 to 616 i/os embedded serdes (latticeecp2m only) data rates 540 mbps to 3.125 gbps 270 mbps with half rate mode up to 16 channels per device pci express, ethernet (1gbe, sgmii), obsai, cpri and serial rapidio. sysdsp block 3 to 42 blocks for high performance multiply and accumulate each block supports one 36x36, four 18x18 or eight 9x9 multipliers flexible memory resources 55kbits to 5308kbits sysmem embedded block ram (ebr) 18kbit block single, pseudo dual and true dual port byte enable mode support 12k to 202kbits distributed ram single port and pseudo dual port sysclock analog plls and dlls two gplls and up to six splls per device clock multiply, divide, phase & delay adjust dynamic pll adjustment two general purpose dlls per device pre-engineered source synchronous i/o ddr registers in i/o cells dedicated gearing logic source synchronous standards support spi4.2, sfi4 (ddr mode), xgmii high speed adc/dac devices dedicated ddr and ddr2 memory support ddr1: 400 (200mhz) / ddr2: 533 (266mhz) dedicated dqs support programmable sysio buffer supports wide range of interfaces lvttl and lvcmos 33/25/18/15/12 sstl 3/2/18 i, ii hstl15 i and hstl18 i, ii pci and differential hstl, sstl lvds, rsds, bus-lvds, mlvds, lvpecl flexible device con?uration 1149.1 boundary scan compliant dedicated bank for con?uration i/os spi boot ?sh interface dual boot images supported transfr i/o for simple ?ld updates soft error detect macro embedded optional bitstream encryption (latticeecp2/m ? versions only) system level support isptracy internal logic analyzer capability on-chip oscillator for initialization & general use 1.2v power supply table 1-1. latticeecp2 (including ?-series? family selection guide device ecp2-6 ecp2-12 ecp2-20 ecp2-35 ecp2-50 ecp2-70 luts (k) 6 12 21 32 48 68 distributed ram (kbits) 12 24 42 64 96 136 ebr sram (kbits) 55 221 276 332 387 1032 ebr sram blocks 3 12 15 18 21 56 sysdsp blocks 36781822 18x18 multipliers 12 24 28 32 72 88 gpll + spll + dll 2+0+2 2+0+2 2+0+2 2+0+2 2+2+2 2+4+2 maximum available i/o 190 297 402 450 500 583 packages and i/o combinations 144-pin tqfp (20 x 20 mm) 90 93 208-pin pqfp (28 x 28 mm) 131 131 256-ball fpbga (17 x 17 mm) 190 193 193 484-ball fpbga (23 x 23 mm) 297 331 331 339 latticeecp2/m family data sheet introduction
1-2 introduction lattice semiconductor latticeecp2/m family data sheet table 1-2. latticeecp2m (including ?-series? family selection guide introduction the latticeecp2/m family of fpga devices has been optimized to deliver high performance features such as advanced dsp blocks, high speed serdes (latticeecp2m family only) and high speed source synchronous inter- faces in an economical fpga fabric. this combination was achieved through advances in device architecture and the use of 90nm technology. the latticeecp2/m fpga fabric was optimized for the new technology from the outset with high performance and low cost in mind. the latticeecp2/m devices include lut-based logic, distributed and embedded memory, phase locked loops (plls), delay locked loops (dlls), pre-engineered source synchronous i/o support, enhanced sysdsp blocks and advanced con?uration support, including encryption (? versions only) and dual boot capabil- ities. the latticeecp2m family of devices features high speed serdes with pcs. these high jitter tolerance and low transmission jitter serdes with pcs blocks can be con?ured to support an array of popular data protocols including pci express, ethernet (1gbe and sgmii), obsai and cpri. transmit pre-emphasis and receive equal- ization settings make serdes suitable for chip to chip and small form factor backplane applications. the isplever design tool from lattice allows large complex designs to be ef?iently implemented using the latticeecp2/m family of fpga devices. synthesis library support for latticeecp2/m is available for popular logic synthesis tools. the isplever tool uses the synthesis tool output along with the constraints from its ?or planning tools to place and route the design in the latticeecp2/m device. the isplever tool extracts the timing from the routing and back-annotates it into the design for timing veri?ation. lattice provides many pre-engineered ip (intellectual property) isplevercore modules for the latticeecp2/m family. by using these ips as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. 672-ball fpbga (27 x 27 mm) 402 450 500 500 900-ball fpbga (31 x 31 mm) 583 device ecp2m20 ecp2m35 ecp2m50 ecp2m70 ecp2m100 luts (k) 19 34 48 67 95 sysmem blocks (18kb) 66 114 225 246 288 embedded memory (kbits) 1217 2101 4147 4534 5308 distributed memory (kbits) 41 71 101 145 202 sysdsp blocks 6 8 22 24 42 18x18 multipliers 24 32 88 96 168 gpll+spll+dll 2+6+2 2+6+2 2+6+2 2+6+2 2+6+2 maximum available i/o 304 410 410 430 616 packages and serdes / i/o combinations 256-ball fpbga (17 x 17 mm) 4 / 140 4 / 140 484-ball fpbga (23 x 23 mm) 4 / 304 4 / 303 4 / 270 672-ball fpbga (27 x 27 mm) 4 / 410 8 / 372 900-ball fpbga (31 x 31 mm) 8 / 410 16 / 416 16 / 416 1152-ball fpbga (35 x 35 mm) 16 / 430 16 / 520 1156-ball fpbga (35 x 35 mm) 16 / 616 table 1-1. latticeecp2 (including ?-series? family selection guide device ecp2-6 ecp2-12 ecp2-20 ecp2-35 ecp2-50 ecp2-70
www.latticesemi.com 2-1 ds1006 architecture_01.5 july 2007 advance data sheet ds1006 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. architecture overview each latticeecp2/m device contains an array of logic blocks surrounded by programmable i/o cells (pic). inter- spersed between the rows of logic blocks are rows of sysmem embedded block ram (ebr) and rows of sys- dsp digital signal processing blocks as shown in the ecp2-6 in figure 2-1. in addition, the latticeecp2m family contain serdes quads in one or more of the corners. figure 2-2 shows the block diagram of ecp2m20 with one quad. there are two kinds of logic blocks, the programmable functional unit (pfu) and programmable functional unit without ram (pff). the pfu contains the building blocks for logic, arithmetic, ram and rom functions. the pff block contains building blocks for logic, arithmetic and rom functions. both pfu and pff blocks are optimized for ?xibility allowing complex designs to be implemented quickly and ef?iently. logic blocks are arranged in a two- dimensional array. only one type of block is used per row. the latticeecp2/m devices contain one or more rows of sysmem ebr blocks. sysmem ebrs are large dedicated 18k fast memory blocks. each sysmem block can be con?ured in variety of depths and widths of ram or rom. in addition, latticeecp2/m devices contain up to two rows of dsp blocks. each dsp block has multipliers and adder/ accumulators, which are the building blocks for complex signal processing capabilities. the latticeecp2m devices feature up to 16 embedded 3.125gbps serdes (serializer / deserializer). each ser- des channel contains independent 8b/10b encoding / decoding, polarity adjust and elastic buffer logic. each group of four serdes along with its physical coding sub-layer (pcs) block creates a quad. the functionality of the serdes/pcs quads can be controlled by memory cells set during device con?uration or by registers addres- sable during device operation. the registers in every quad can be programmed by a soft ip interface, referred to as the serdes client interface (sci). these quads (up to four) are located at the corners of the devices. each pic block encompasses two pios (pio pairs) with their respective sysio buffers. the sysio buffers of the latticeecp2/m devices are arranged into eight banks, allowing the implementation of a wide variety of i/o stan- dards. in addition, a separate i/o bank is provided for the programming interfaces. pio pairs on the left and right edges of the device can be con?ured as lvds transmit/receive pairs. the pic logic also includes pre-engineered support to aid in the implementation of the high speed source synchronous standards such as spi4.2 along with memory interfaces including ddr2. other blocks provided include plls, dlls and con?uration functions. the latticeecp2/m architecture provides two general plls (gpll) and up to six standard plls (spll) per device. in addition, each latticeecp2/m family member provides two dlls per device. the gplls and dlls blocks are located in pairs at the end of the bottom- most ebr row; the dll block located towards the edge of the device. the spll blocks are located at the end of the other ebr/dsp rows. the con?uration block that supports features such as con?uration bit-stream decryption, transparent updates and dual boot support is located toward the center of this ebr row. every device in the latticeecp2/m family sup- ports a sysconfig port located in the corner between banks four and ?e, which allows for serial or parallel device con?uration. in addition, every device in the family has a jtag port. this family also provides an on-chip oscillator and soft error detect capability. the latticeecp2/m devices use 1.2v as their core voltage. latticeecp2/m family data sheet architecture
2-2 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-1. simpli?d block diagram, ecp2-6 device (top level) figure 2-2. simpli?d block diagram, ecp2m20 device (top level) programmable function units (pfus) flexible sysio buffers: lvcmos, hstl, sstl, lvds, and other standards sysdsp blocks multiply and accumulate support sysmem block ram 18kbit dual port sysclock plls and dlls frequency synthesis and clock alignment flexible routing optimized for speed, cost and routability configuration logic, including dual boot and encryption. on-chip oscillator and soft-error detection. configuration port pre-engineered source synchronous support ?ddr1/2 ?spi4.2 ?adc/dac devices flexi b le sysio b u ffers: l v cmos, hstl sstl, l v ds pre-engineered so u rce synchrono u s s u pport ?ddr1/2 ?spi4.2 ?adc/dac de v ices serdes dsp blocks m u ltiply & acc u m u late s u pport on-chip oscillator programma b le f u nction units (pfus) channel 3 channel 2 channel 1 channel 0 sysmem block ram 1 8 k b it d u al port config u ration logic, incl u ding d u al b oot and encryption, and soft-error detection flexi b le ro u ting optimized for speed, cost & ro u ta b ility sysclock gplls & gdlls fre qu ency synthesis & clock alignment config u ration port sysclock splls
2-3 architecture lattice semiconductor latticeecp2/m family data sheet pfu blocks the core of the latticeecp2/m device consists of pfu blocks which are provided in two forms, the pfu and pff. the pfus can be programmed to perform logic, arithmetic, distributed ram and distributed rom functions. pff blocks can be programmed to perform logic, arithmetic and rom functions. except where necessary, the remain- der of this data sheet will use the term pfu to refer to both pfu and pff blocks. each pfu block consists of four interconnected slices, numbered 0-3 as shown in figure 2-3. all the interconnec- tions to and from pfu blocks are from routing. there are 50 inputs and 23 outputs associated with each pfu block. figure 2-3. pfu diagram slice slice 0 through slice 2 contain two lut4s feeding two registers, whereas slice 3 contains two lut4s only. for pfus, slice 0 and slice 2 can also be con?ured as distributed memory, a capability not available in the pff. table 2-1 shows the capability of the slices in both pff and pfu blocks along with the operation modes they enable. in addition, each pfu contains some logic that allows the luts to be combined to perform functions such as lut5, lut6, lut7 and lut8. there is control logic to perform set/reset functions (programmable as synchro- nous/asynchronous), clock select, chip-select and wider ram/rom functions. figure 2-4 shows an overview of the internal logic of the slice. the registers in the slice can be con?ured for positive/negative and edge triggered or level sensitive clocks. table 2-1. resources and modes available per slice slices 0, 1 and 2 have 14 input signals: 13 signals from routing and one from the carry-chain (from the adjacent slice or pfu). there are seven outputs: six to routing and one to carry-chain (to the adjacent pfu). slice 3 has 13 input signals from routing and four signals to routing. table 2-2 lists the signals associated with slice 0 to slice 2. slice pfu block pff block resources modes resources modes slice 0 2 lut4s and 2 registers logic, ripple, ram, rom 2 lut4s and 2 registers logic, ripple, rom slice 1 2 lut4s and 2 registers logic, ripple, rom 2 lut4s and 2 registers logic, ripple, rom slice 2 2 lut4s and 2 registers logic, ripple, ram, rom 2 lut4s and 2 registers logic, ripple, rom slice 3 2 lut4s logic, rom 2 lut4s logic, rom slice 0 lut4 & carry lut4 & carry d d slice 1 lut4 & carry lut4 & carry slice 2 lut4 & carry lut4 & carry from routing to routing slice 3 lut4 lut4 d d d d ff ff ff ff ff ff
2-4 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-4. slice diagram table 2-2. slice signal descriptions function type signal names description input data signal a0, b0, c0, d0 inputs to lut4 input data signal a1, b1, c1, d1 inputs to lut4 input multi-purpose m0 multipurpose input input multi-purpose m1 multipurpose input input control signal ce clock enable input control signal lsr local set/reset input control signal clk system clock input inter-pfu signal fc fast carry-in 1 input inter-slice signal fxa intermediate signal to generate lut6 and lut7 input inter-slice signal fxb intermediate signal to generate lut6 and lut7 output data signals f0, f1 lut4 output register bypass signals output data signals q0, q1 register outputs output data signals ofx0 output of a lut5 mux output data signals ofx1 output of a lut6, lut7, lut8 2 mux depending on the slice output inter-pfu signal fco slice 2 of each pfu is the fast carry chain output 1 1. see figure 2-4 for connection details. 2. requires two pfus. lut4 & carry* lut4 & carry* slice a0 c0 d0 ff* ofx0 f0 q0 a1 b1 c1 d1 ci ci co co ce clk lsr ff* ofx1 f1 q1 f/sum f/sum d d m1 fci from different slice/pfu fco to different slice/pfu lut5 m u x m0 from routin g to routin g fxb fxa b0 for slices 0 and 2, memory control signals are generated from slice 1 as follo w s: wck is clk wre is from lsr di[3:2] for slice 2 and di[1:0] for slice 0 data wad [a:d] is a 4 b it address from slice 1 lut inp u t * n ot in slice 3
2-5 architecture lattice semiconductor latticeecp2/m family data sheet modes of operation each slice has up to four potential modes of operation: logic, ripple, ram and rom. logic mode in this mode, the luts in each slice are con?ured as 4-input combinatorial lookup tables. a lut4 can have 16 possible input combinations. any four input logic functions can be generated by programming this lookup table. since there are two lut4s per slice, a lut5 can be constructed within one slice. larger look-up tables such as lut6, lut7 and lut8 can be constructed by concatenating other slices. note lut8 requires more than four slices. ripple mode ripple mode supports the ef?ient implementation of small arithmetic functions. in ripple mode, the following func- tions can be implemented by each slice: addition 2-bit subtraction 2-bit add/subtract 2-bit using dynamic control up counter 2-bit down counter 2-bit up/down counter with async clear up/down counter with preload (sync) ripple mode multiplier building block multiplier support comparator functions of a and b inputs a greater-than-or-equal-to b a not-equal-to b a less-than-or-equal-to b ripple mode includes an optional con?uration that performs arithmetic using fast carry chain methods. in this con- ?uration (also referred to as ccu2 mode) two additional signals, carry generate and carry propagate, are gener- ated on a per slice basis to allow fast arithmetic functions to be constructed by concatenating slices. ram mode in this mode, a 16x4-bit distributed single port ram (spr) can be constructed using each lut block in slice 0 and slice 2 as a 16x1-bit memory. slice 1 is used to provide memory address and control signals. a 16x2-bit pseudo dual port ram (pdpr) memory is created by using one slice as the read-write port and the other companion slice as the read-only port. the lattice design tools support the creation of a variety of different size memories. w here appropriate, the soft- ware will construct these using distributed memory primitives that represent the capabilities of the pfu. table 2-3 shows the number of slices required to implement different distributed ram primitives. for more information on using ram in latticeecp2/m devices, please see details of additional technical documentation at the end of this data sheet. table 2-3. number of slices required to implement distributed ram spr 16x4 pdpr 16x4 number of slices 3 3 note: spr = single port ram, pdpr = pseudo dual port ram
2-6 architecture lattice semiconductor latticeecp2/m family data sheet rom mode rom mode uses the lut logic; hence, slices 0 through 3 can be used in rom mode. preloading is accomplished through the programming interface during pfu con?uration. routing there are many resources provided in the latticeecp2/m devices to route signals individually or as busses with related control signals. the routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. the inter-pfu connections are made with x1 (spans two pfu), x2 (spans three pfu) and x6 (spans seven pfu). the x1 and x2 connections provide fast and ef?ient connections in horizontal and vertical directions. the x2 and x6 resources are buffered allowing both short and long connections routing between pfus. the latticeecp2/m family has an enhanced routing architecture that produces a compact design. the isplever design tool takes the output of the synthesis tool and places and routes the design. generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. sysclock phase locked loops (gpll/spll) the sysclock plls provide the ability to synthesize clock frequencies. all the devices in the latticeecp2/m fam- ily support two general purpose plls (gplls) which are full-featured plls. in addition, some of the larger devices have two to six standard plls (splls) that have a subset of gpll functionality. general purpose pll (gpll) the architecture of the gpll is shown in figure 2-5. a description of the gpll functionality follows. clki is the reference frequency (generated either from the pin or from routing) for the pll. clki feeds into the input clock divider block. the clkfb is the feedback signal (generated from clkop or from a user clock pin/ logic). this signal feeds into the feedback divider. the feedback divider is used to multiply the reference fre- quency. the delay adjust block adjusts either the delays of the reference or feedback signals. the delay adjust block can either be programmed during con?uration or can be adjusted dynamically. the setup, hold or clock-to-out times of the device can be improved by programming a delay in the feedback or input path of the pll which will advance or delay the output clock with reference to the input clock. following the delay adjust block, both the input path and feedback signals enter the voltage controlled oscillator (vco) block. in this block the difference between the input path and feedback signals is used to control the fre- quency and phase of the oscillator. a lock signal is generated by the vco to indicate that vco has locked onto the input clock signal. in dynamic mode, the pll may lose lock after a dynamic delay adjustment and not relock until the t lock parameter has been satis?d. latticeecp2/m devices have two dedicated pins on the left and right edges of the device for connecting optional external capacitors to the vco. this allows the plls to operate at a lower frequency. this is a shared resource which can only be used by one pll (gpll or spll) per side. the output of the vco then enters the post-scalar divider. the post-scalar divider allows the vco to operate at higher frequencies than the clock output (clkop), thereby increasing the frequency range. a secondary divider takes the clkop signal and uses it to derive lower frequency outputs (clkok). the phase/duty select block adjusts the phase and duty cycle of the clkop signal and generates the clkos signal. the phase/duty cycle set- ting can be pre-programmed or dynamically adjusted. the primary output from the post scalar divider clkop along with the outputs from the secondary divider (clkok) and phase/duty select (clkos) are fed to the clock distribution network.
2-7 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-5. general purpose pll (gpll) diagram standard pll (spll) some of the larger devices have two to six standard plls (splls). splls have the same features as gplls but without delay adjustment capability. splls also provide different parametric speci?ations. for more information, please see details of additional technical documentation at the end of this data sheet. table 2-4 provides a description of the signals in the gpll and spll blocks. table 2-4. gpll and spll blocks signal descriptions signal i/o description clki i clock input from external pin or routing clkfb i pll feedback input from clkop (pll internal), from clock net (clkop) or from a user clock (pin or logic) rst i ? to reset pll counters, vco, charge pumps and m-dividers rstk i ? to reset k-divider clkos o pll output clock to clock tree (phase shifted/duty cycle changed) clkop o pll output clock to clock tree (no phase shift) clkok o pll output to clock tree through secondary clock divider lock o ? indicates pll lock to clki ddamode 1 i dynamic delay enable. ?? pin control (dynamic), ?? fuse control (static) ddaizr 1 i dynamic delay zero. ?? delay = 0, ?? delay = on ddailag 1 i dynamic delay lag/lead. ?? lead, ?? lag ddaidel[2:0] 1 i dynamic delay input dpa modes i dpa (dynamic phase adjust/duty cycle select) mode dphase [3:0] i dpa phase adjust inputs ddduty [3:0] dpa duty cycle select inputs 1. these signals are not available in spll. inp u t clock di v ider (clki) feed b ack di v ider (clkfb) delay adj u st v oltage controlled oscillator post scalar di v ider (clkop) phase/d u ty select secondary di v ider (clkok) clkos clkok clkop lock clkfb clki rst dynamic delay adj u stment (from ro u ting or external pin) from clkop (pll internal), from clock net(clkop) or from a u ser clock (pin or logic) dynamic adj u stment pllcap external pin (optional external capacitor) rstk
2-8 architecture lattice semiconductor latticeecp2/m family data sheet delay locked loops (dll) in addition to plls, the latticeecp2/m family of devices has two dlls per device. clki is the input frequency (generated either from the pin or routing) for the dll. clki feeds into the output muxes block to bypass the dll, directly to the delay chain block and (directly or through divider circuit) to the reference input of the phase frequency detector (pfd) input mux. the reference signal for the pfd can also be generated from the delay chain and clkfb signals. the feedback input to the pfd is generated from the clkfb pin, clki or from tapped signal from the delay chain. the pfd produces a binary number proportional to the phase and frequency difference between the reference and feedback signals. this binary output of the pfd is feed into a arithmetic logic unit (alu). based on these inputs, the alu determines the correct digital control codes to send to the delay chain in order to better match the refer- ence and feedback signals. this digital code from the alu is also transmitted via the digital control bus (dcntl) bus to its associated dlldela delay block. the aluhold input allows the user to suspend the alu output at its current value. the uddcntl signal allows the user to latch the current value on the dcntl bus. the dll has two independent clock outputs, clkop and clkos. these outputs can individually select one of the outputs from the tapped delay line. the clkos has optional ?e phase shift and divider blocks to allow this output to be further modi?d, if required. the ?e phase shift block allows the clkos output to phase shifted a further 45, 22.5 or 11.25 degrees relative to its normal position. both the clkos and clkop outputs are available with optional duty cycle correction. divide by two and divide by four frequencies are available at clkos. the lock out- put signal is asserted when the dll is locked. figure 2-6 shows the dll block diagram and table 2-5 provides a description of the dll inputs and outputs. the user can con?ure the dll for many common functions such as time reference delay mode and clock injection removal mode. lattice provides primitives in its design tools for these functions. for more information on the dll, please see details of additional technical documentation at the end of this data sheet. figure 2-6. delay locked loop diagram (dll) clkop clkos lock clkfb clki aluhold dc n tl uddc n tl phase frequency detector delay3 delay2 delay1 delay0 delay4 reference feed b ack 9 ? ? ? ? rst n (from ro u ting or external pin) from clkop (dll internal), from clock net (clkop) or from a u ser clock (pin or logic) arithmetic lo g ic unit lock detect di g ital control output delay chain output muxes duty cycle 50% duty cycle 50%
2-9 architecture lattice semiconductor latticeecp2/m family data sheet table 2-5. dll signals dlldela delay block closely associated with each dll is a dlldela block. this is a delay block consisting of a delay line with taps and a selection scheme that selects one of the taps. the dcntl[8:0] bus controls the delay of the clko signal. typi- cally this is the delay setting that the dll uses to achieve phase alignment. this results in the delay providing a cal- ibrated 90?phase shift that is useful in centering a clock in the middle of a data cycle for source synchronous data. the clko signal feeds the edge clock network. figure 2-7 shows the connections between the dll block and the dlldela delay block. for more information, please see details of additional technical documentation at the end of this data sheet. figure 2-7. dlldela delay block pll/dll cascading latticeecp2/m devices have been designed to allow certain combinations of pll (gpll and spll) and dll cas- cading. the allowable combinations are as follows: pll to pll supported pll to dll supported signal i/o description clki i clock input from external pin or routing clkfb i dll feed input from dll output, clock net, routing or external pin rstn i active low synchronous reset aluhold i active high freezes the alu uddcntl i synchronous enable signal (hold high for two cycles) from routing dcntl[8:0] o encoded digital control signals for pic indel and slave delay calibration clkop o the primary clock output clkos o the secondary clock output with ?e phase shift and/or division by 2 or by 4 lock o active high phase lock indicator dll block clkop clkos lock clko clki clkfb clki dlldela delay block pll_pio dll_pio ro u ting ro u ting clkfb_ck eclk1 clkop gdllfb_pio dc n tl[ 8 :0] * * * * soft w are selecta b le
2-10 architecture lattice semiconductor latticeecp2/m family data sheet the dlls in the latticeecp2/m are used to shift the clock in relation to the data for source synchronous inputs. plls are used for frequency synthesis and clock generation for source synchronous interfaces. cascading pll and dll blocks allows applications to utilize the unique bene?s of both dlls and plls. for further information on the dll, please see details of additional technical documentation at the end of this data sheet. gpll/spll/gdll pio input pin connections (latticeecp2m family only) all latticeecp2m devices contain two gdlls, two gplls and six splls, arranged in quadrants as shown in figure 2-8. in the latticeecp2m devices gplls, splls and gdlls share their input pins. figure 2-8 shows the sharing of splls input pin connections in the upper two quadrants and the sharing of gdll, gpll and spll input pin connections in the lower two quadrants. figure 2-8. sharing of pio pins by gpll, spll and gdll in latticeecp2m devices clock dividers latticeecp2/m devices have two clock dividers, one on the left side and one on the right side of the device. these are intended to generate a slower-speed system clock from a high-speed edge clock. the block operates in a ?, ? or ? mode and maintains a known phase relationship between the divided down clock and the high-speed clock based on the release of its reset signal. the clock dividers can be fed from selected pll/dll outputs, dll- dela delay blocks, routing or from an external clock input. the clock divider outputs serve as primary clock sources and feed into the clock distribution network. the reset (rst) control signal resets input and synchro- nously forces all outputs to low. the release signal releases outputs synchronously to the input clock. for further information on clock dividers, please see details of additional technical documentation at the end of this data sheet. figure 2-9 shows the clock divider connections. spll spll gpll gdll spll spll_pio spll_pio gpll_pio gdll_pio spll_pio spll spll gpll gdll spll spll_pio spll_pio gpll_pio gdll_pio spll_pio upper left q u adrant lo w er left q u adrant upper right q u adrant lo w er right q u adrant
2-11 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-9. clock divider connections clock distribution network latticeecp2/m devices have eight quadrant-based primary clocks and eight ?xible region-based secondary clocks/control signals. two high performance edge clocks are available on each edge of the device to support high speed interfaces. these clock inputs are selected from external i/os, the sysclock plls, dlls or routing. these clock inputs are fed throughout the chip via a clock distribution system. primary clock sources latticeecp2/m devices derive clocks from ?e primary sources: pll (gpll and spll) outputs, dll outputs, clkdiv outputs, dedicated clock inputs and routing. latticeecp2/m devices have two to eight sysclock plls and two dlls, located on the left and right sides of the device. there are eight dedicated clock inputs, two on each side of the device, with the exception of the latticeecp2m 256-fpbga package devices which have six dedicated clock inputs on the device. figure 2-10 shows the primary clock sources. rst release ? ? ? 8 clko clkop (gpll) clkop (dll) ro u ting pll pad clkos (gpll) clkos (dll) clkdiv
2-12 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-10. primary clock sources for ecp2-50 primary clock sources to ei g ht quadrant clock selection from ro u ting from ro u ting spll gpll dll pll inp u t pll inp u t dll inp u t n ote: this diagram sho w s so u rces for the ecp2-50 de v ice. smaller latticeecp2 de v ices ha v e fe w er splls. all latticeecp2m de v ic e ha v e six splls. clk div clock inp u t clock inp u t pll inp u t pll inp u t dll inp u t clock inp u t clock inp u t clock inp u t clock inp u t clock inp u t clock inp u t spll gpll dll clk div
2-13 architecture lattice semiconductor latticeecp2/m family data sheet secondary clock/control sources latticeecp2/m devices derive secondary clocks (sc0 through sc7) from eight dedicated clock input pads and the rest from routing. figure 2-11 shows the secondary clock sources. figure 2-11. secondary clock sources secondary clock sources from routing from routing from routing from routing from routing from routing from routing from routing from routing from routing clock inp u t clock inp u t clock inp u t clock inp u t clock inp u t clock inp u t from routing from routing from routing from routing clock inp u t clock inp u t from routing from routing
2-14 architecture lattice semiconductor latticeecp2/m family data sheet edge clock sources edge clock resources can be driven from a variety of sources at the same edge. edge clock resources can be driven from adjacent edge clock pios, primary clock pios, plls/dlls and clock dividers as shown in figure 2-12. figure 2-12. edge clock sources ei g ht ed g e clocks (eclk) two clocks per ed g e so u rces for b ottom edge clocks so u rces for right edge clocks clock inp u t clock inp u t from ro u ting from ro u ting from ro u ting from ro u ting from ro u ting clock inp u t clock inp u t clock inp u t clock inp u t from ro u ting from ro u ting clock inp u t clock inp u t from ro u ting so u rces for left edge clocks so u rces for top edge clocks dll inp u t pll inp u t dll inp u t pll inp u t dlldela dll gpll dll gpll dlldela
2-15 architecture lattice semiconductor latticeecp2/m family data sheet primary clock routing the clock routing structure in latticeecp2/m devices consists of a network of eight primary clock lines (clk0 through clk7) per quadrant. the primary clocks of each quadrant are generated from muxes located in the center of the device. all the clock sources are connected to these muxes. figure 2-13 shows the clock routing for one quadrant. each quadrant mux is identical. if desired, any clock can be routed globally figure 2-13. per quadrant primary clock selection dynamic clock select (dcs) the dcs is a smart multiplexer function available in the primary clock routing. it switches between two independent input clock sources without any glitches or runt pulses. this is achieved irrespective of when the select signal is toggled. there are two dcs blocks per quadrant; in total, eight dcs blocks per device. the inputs to the dcs block come from the center muxes. the output of the dcs is connected to primary clocks clk6 and clk7 (see figure 2- 13). figure 2-14 shows the timing waveforms of the default dcs operating mode. the dcs block can be programmed to other modes. for more information on the dcs, please see details of additional technical documentation at the end of this data sheet. figure 2-14. dcs waveforms secondary clock/control routing secondary clocks in the latticeecp2 devices are region-based resources. ebr/dsp rows and a special vertical routing channel bound the secondary clock regions. this special vertical routing channel aligns with either the left edge of the center dsp block in the dsp row or the center of the dsp row. figure 2-15 shows this special vertical routing channel and the eight secondary clock regions for the ecp2-50. latticeecp2 devices have eight second- ary clock and control signal resources per region (sc0 to sc7). clk0 clk1 clk2 clk3 clk4 clk5 clk6 clk7 35:1 35:1 35:1 35:1 32:1 32:1 32:1 32:1 35:1 35:1 8 primary clocks (clk0 to clk7) per q u adrant dcs dcs primary clock feedlines: plls + dlls + clkdi v s + pios + ro u ting clk0 sel dcsout clk1
2-16 architecture lattice semiconductor latticeecp2/m family data sheet the secondary clock muxes are located in the center of the device. figure 2-16 shows the mux structure of the secondary clock routing. figure 2-15. secondary clock regions ecp2-50 figure 2-16. per region secondary clock selection i/o bank 0 i/o bank 1 i/o bank 6 i/o bank 7 i/o bank 2 i/o bank 3 i/o bank 5 i/o bank 4 secondary clock region 1 secondary clock region 2 secondary clock region 3 secondary clock region 4 secondary clock region 5 secondary clock region 6 secondary clock region 7 secondary clock region 8 v ertical ro u ting channel regional bo u ndary ebr ro w regional bo u ndary dsp ro w regional bo u ndary dsp ro w regional bo u ndary bank 8 sc0 sc1 sc2 sc3 sc4 sc5 24:1 24:1 24:1 24:1 sc6 24:1 sc7 24:1 24:1 24:1 8 secondary clocks (sc0 to sc7) per region clock/control secondary clock feedlines: 8 pios + 16 ro u ting
2-17 architecture lattice semiconductor latticeecp2/m family data sheet slice clock selection figure 2-17 shows the clock selections and figure 2-18 shows the control selections for slice0 through slice2. all the primary clocks and the four secondary clocks are routed to this clock selection mux. other signals via routing can be used as a clock input to the slices. slice controls are generated from the secondary clocks or other signals connected via routing. if none of the signals are selected for both clock and control then the default value of the mux output is 1. slice 3 does not have any registers; therefore it does not have the clock or control muxes. figure 2-17. slice0 through slice2 clock selection figure 2-18. slice0 through slice2 control selection edge clock routing latticeecp2/m devices have a number of high-speed edge clocks that are intended for use with the pios in the implementation of high-speed interfaces. there are eight edge clocks per device: two edge clocks per edge. differ- ent pll and dll outputs are routed to the two muxes on the left and right sides of the device. in addition, the clko signal (generated from the dlldela block) is routed to all the edge clock muxes on the left and right sides of the device. figure 2-19 shows the selection muxes for these clocks. clock to slice primary clock secondary clock ro u ting v cc 8 4 12 1 25:1 slice control secondary clock ro u ting v cc 3 12 1 16:1
2-18 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-19. edge clock mux connections sysmem memory latticeecp2/m devices contains a number of sysmem embedded block ram (ebr). the ebr consists of an 18- kbit ram with dedicated input and output registers. sysmem memory block the sysmem block can implement single port, dual port or pseudo dual port memories. each block can be used in a variety of depths and widths as shown in table 2-6. fifos can be implemented in sysmem ebr blocks by imple- menting support logic with pfus. the ebr block facilitates parity checking by supporting an optional parity bit for each data byte. ebr blocks provide byte-enable support for con?urations with18-bit and 36-bit data widths. left and right edge clocks eclk1 top and bottom edge clocks eclk1/ eclk2 clock inp u t pad ro u ting ro u ting inp u t pad gpll inp u t pad dll o u tp u t clkop gpll o u tp u t clkop clko left and right edge clocks eclk2 ro u ting inp u t pad gpll inp u t pad dll o u tp u t clkos gpll o u tp u t clkos clko (both m u x)
2-19 architecture lattice semiconductor latticeecp2/m family data sheet table 2-6. sysmem block con?urations bus size matching all of the multi-port memory modes support different widths on each of the ports. the ram bits are mapped lsb word 0 to msb word 0, lsb word 1 to msb word 1, and so on. although the word size and number of words for each port varies, this mapping scheme applies to each port. ram initialization and rom operation if desired, the contents of the ram can be pre-loaded during device con?uration. by preloading the ram block during the chip con?uration cycle and disabling the write controls, the sysmem block can also be utilized as a rom. memory cascading larger and deeper blocks of rams can be created using ebr sysmem blocks. typically, the lattice design tools cascade memory transparently, based on speci? design inputs. single, dual and pseudo-dual port modes in all the sysmem ram modes the input data and address for the ports are registered at the input of the memory array. the output data of the memory is optionally registered at the output. ebr memory supports three forms of write behavior for single port or dual port operation: 1. normal ?data on the output appears only during a read cycle. during a write cycle, the data (at the current address) does not appear on the output. this mode is supported for all data widths. 2. w rite through ?a copy of the input data appears at the output of the same port during a write cycle. this mode is supported for all data widths. 3. read-before- w rite ? w hen new data is being written, the old content of the address appears at the output. this mode is supported for x9, x18 and x36 data widths. memory core reset the memory array in the ebr utilizes latches at the a and b output ports. these latches can be reset asynchro- nously or synchronously. rsta and rstb are local signals, which reset the output latches associated with port a and port b respectively. the global reset (gsrn) signal resets both ports. the output data latches and associated resets for both ports are as shown in figure 2-20. memory mode con?urations single port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36 true dual port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 pseudo dual port 16,384 x 1 8,192 x 2 4,096 x 4 2,048 x 9 1,024 x 18 512 x 36
2-20 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-20. memory core reset for further information on the sysmem ebr block, please see the details of additional technical documentation at the end of this data sheet. ebr asynchronous reset ebr asynchronous reset or gsr (if used) can only be applied if all clock enables are low for a clock cycle before the reset is applied and released a clock cycle after the reset is released, as shown in figure 2-21. the gsr input to the ebr is always asynchronous. figure 2-21. ebr asynchronous reset (including gsr) timing diagram if all clock enables remain enabled, the ebr asynchronous reset or gsr may only be applied and released after the ebr read and write clock inputs are in a steady state condition for a minimum of 1/f max (ebr clock). the reset release must adhere to the ebr synchronous reset setup time before the next active read or write clock edge. if an ebr is pre-loaded during con?uration, the gsr input must be disabled or the release of the gsr during device w ake up must occur before the release of the device i/os becoming active. these instructions apply to all ebr ram and rom implementations. note that there are no reset restrictions if the ebr synchronous reset is used and the ebr gsr input is disabled. sysdsp block the latticeecp2/m family provides a sysdsp block making it ideally suited for low cost, high performance digital signal processing (dsp) applications. typical functions used in these applications are finite impulse response q set d l clr output data latches memory core port a[17:0] q set d port b[17:0] rstb gsrn pro g rammable disable rsta l clr reset clock clock ena b le
2-21 architecture lattice semiconductor latticeecp2/m family data sheet (fir) ?ters, fast fourier transforms (fft) functions, correlators, reed-solomon/turbo/convolution encoders and decoders. these complex signal processing functions use similar building blocks such as multiply-adders and mul- tiply-accumulators. sysdsp block approach compare to general dsp conventional general-purpose dsp chips typically contain one to four (multiply and accumulate) mac units with ?ed data-width multipliers; this leads to limited parallelism and limited throughput. their throughput is increased by higher clock speeds. the latticeecp2/m, on the other hand, has many dsp blocks that support different data- widths. this allows the designer to use highly parallel implementations of dsp functions. the designer can opti- mize the dsp performance vs. area by choosing appropriate level of parallelism. figure 2-22 compares the fully serial and the mixed parallel and serial implementations. figure 2-22. comparison of general dsp and latticeecp2/m approaches sysdsp block capabilities the sysdsp block in the latticeecp2/m family supports four functional elements in three 9, 18 and 36 data path widths. the user selects a function element for a dsp block and then selects the width and type (signed/unsigned) of its operands. the operands in the latticeecp2/m family sysdsp blocks can be either signed or unsigned but not mixed within a function element. similarly, the operand widths cannot be mixed within a block. in latticeecp2/m family of devices the dsp elements can be concatenated. the resources in each sysdsp block can be con?ured to support the following four elements: mult (multiply) mac (multiply, accumulate) multaddsub (multiply, addition/subtraction) multaddsubsum (multiply, addition/subtraction, accumulate) the number of elements available in each block depends in the width selected from the three available options x9, x18, and x36. a number of these elements are concatenated for highly parallel implementations of dsp functions. table 2-7 shows the capabilities of the block. multiplier 0 x operand a operand b x operand a operand b x operand a operand b multiplier 1 multiplier k (k adds) output m/k loops single multiplier x operand a accumulator operand b m loops function implemented in general purpose dsp function implemented in latticeecp2/m m/k accumulate + +
2-22 architecture lattice semiconductor latticeecp2/m family data sheet table 2-7. maximum number of elements in a block some options are available in four elements. the input register in all the elements can be directly loaded or can be loaded as shift register from previous operand registers. by selecting ?ynamic operation the following operations are possible: in the ?igned/unsigned options the operands can be switched between signed and unsigned on every cycle. in the ?dd/sub option the accumulator can be switched between addition and subtraction on every cycle. the loading of operands can switch between parallel and serial operations. mult sysdsp element this multiplier element implements a multiply with no addition or accumulator nodes. the two operands, a and b, are multiplied and the result is available at the output. the user can enable the input/output and pipeline registers. figure 2-23 shows the mult sysdsp element. figure 2-23. mult sysdsp element width of multiply x9 x18 x36 mult 8 4 1 mac 2 2 multaddsub 4 2 multaddsubsum 2 1 multiplier x n m m n m n m n n m m+n m+n (default) clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) pipeline register input register multiplier multiplicand signed a shift register a in shift register b in shift register a out shift register b out output input data register a input data register b output register to multiplier input register signed b to multiplier
2-23 architecture lattice semiconductor latticeecp2/m family data sheet mac sysdsp element in this case, the two operands, a and b, are multiplied and the result is added with the previous accumulated value. this accumulated value is available at the output. the user can enable the input and pipeline registers but the out- put register is always enabled. the output register is used to store the accumulated value. the accumulators in the dsp blocks in latticeecp2/m family can be initialized dynamically. a registered over?w signal is also available. the over?w conditions are provided later in this document. figure 2-24 shows the mac sysdsp element. figure 2-24. mac sysdsp multiplier x input data register a n m input data register b m n n n m n n m output register out put register accumulator multiplier multiplicand signed a serial register b in serial register a in srob sroa output addn accumsload pipeline clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) input pipeline register input register pipeline register input register pipeline register to accumulator signed b pipeline input to accumulator to accumulator to accumulator overflow signal m+n (default) m+n+16 (default) m+n+16 (default) preload register register register register
2-24 architecture lattice semiconductor latticeecp2/m family data sheet multaddsub sysdsp element in this case, the operands a0 and b0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands a1 and a2. the user can enable the input, output and pipeline registers. figure 2-25 shows the multaddsub sysdsp element. figure 2-25. multaddsub multiplier multiplier add/sub pipe reg pipe reg n m m n m n m n n m m+n (default) m+n+1 (default) m+n+1 (default) m+n (default) x x n m m n m n n m multiplier b0 multiplicand a0 multiplier b1 multiplicand a1 signed a shift register a in shift register b in shift register a out shift register b out output addn pipeline register clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) input register pipeline register input register pipeline register pipeline register pipe reg signed b pipeline register input register input data register a input data register a input data register b input data register b output register to add/sub to add/sub to add/sub
2-25 architecture lattice semiconductor latticeecp2/m family data sheet multaddsubsum sysdsp element in this case, the operands a0 and b0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands a1 and b1. additionally the operands a2 and b2 are multiplied and the result is added/ subtracted with the result of the multiplier operation of operands a3 and b3. the result of both addition/subtraction are added in a summation block. the user can enable the input, output and pipeline registers. figure 2-26 shows the multaddsubsum sysdsp element. figure 2-26. multaddsubsum clock, clock enable and reset resources global clock, clock enable and reset signals from routing are available to every dsp block. four clock, reset and clock enable signals are selected for the sysdsp block. from four clock sources (clk0, clk1, clk2, clk3) one clock is selected for each input register, pipeline register and output register. similarly clock enable (ce) and multiplier add/sub0 x n m m+n (default) m+n (default) m+n+1 m+n+2 m+n+2 m+n+1 m+n (default) m+n (default) m n m n m n n m x n n m n n m multiplier multiplier multiplier add/sub1 x n m m n m n m n n m x n m m n m n n m sum multiplier b0 multiplicand a0 multiplier b1 multiplicand a1 multiplier b2 multiplicand a2 multiplier b3 multiplicand a3 signed a shift register b in output addn0 pipeline register clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) input register pipeline register input register to add/sub0 to add/sub0, add/sub1 pipeline register signed b pipeline register input register to add/sub0, add/sub1 pipeline register input register to add/sub1 addn1 pipeline register pipeline register pipeline register shift register a in shift register b out shift register a out input data register a input data register a input data register a input data register a input data register b input data register b input data register b input data register b output register
2-26 architecture lattice semiconductor latticeecp2/m family data sheet reset (rst) are selected from their four respective sources (ce0, ce1, ce2, ce3 and rst0, rst1, rst2, rst3) at each input register, pipeline register and output register. signed and unsigned with different widths the dsp block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. for unsigned operands, unused upper data bits should be ?led to create a valid x9, x18 or x36 operand. for signed twos complement operands, sign extension of the most signi?ant bit should be performed until x9, x18 or x36 width is reached. table 2-8 provides an example of this. table 2-8. sign extension example overflow flag from mac the sysdsp block provides an over?w output to indicate that the accumulator has over?wed. w hen two unsigned numbers are added and the result is a smaller number than the accumulator, ?oll-over is said to have occurred and an over?w signal is indicated. w hen two positive numbers are added with a negative sum and when two negative numbers are added with a positive sum, then the accumulator ?oll-over is said to have occurred and an over?w signal is indicated. note that when over?w occurs the over?w ?g is present for only one cycle. by counting these over?w pulses in fpga logic, larger accumulators can be constructed. the conditions over?w signal for signed and unsigned operands are listed in figure 2-27. figure 2-27. accumulator over?w/under?w number unsigned unsigned 9-bit unsigned 18-bit signed twos complement signed 9 bits twos complement signed 18 bits +5 0101 000000101 000000000000000101 0101 000000101 000000000000000101 -6 n/a n/a n/a 1010 111111010 111111111111111010 000000000 000000001 000000010 000000011 111111101 111111110 111111111 overflow signal is generated for one cycle when this boundary is crossed 0 +1 +2 +3 -3 -2 -1 unsigned operation signed operation 0101111111 0101111110 0101111101 0101111100 1010000010 1010000001 1010000000 255 254 253 252 -254 -255 -256 000000000 000000001 000000010 000000011 111111101 111111110 111111111 carry signal is generated for one cycle when this boundary is crossed 0 1 2 3 509 510 511 0101111111 0101111110 0101111101 0101111100 1010000010 1010000001 1010000000 255 254 253 252 258 257 256
2-27 architecture lattice semiconductor latticeecp2/m family data sheet ipexpress the user can access the sysdsp block via the isplever ipexpress tool which provides the option to con?ure each dsp module (or group of modules) or by direct hdl instantiation. in addition, lattice has partnered with the math w orks to support instantiation in the simulink tool, a graphical simulation environment. simulink works with isplever to dramatically shorten the dsp design cycle in lattice fpgas. optimized dsp functions lattice provides a library of optimized dsp ip functions. some of the ip cores planned for the latticeecp2/m dsp include the bit correlator, fast fourier transform, finite impulse response (fir) filter, reed-solomon encoder/ decoder, turbo encoder/decoder and convolutional encoder/decoder. please contact lattice to obtain the latest list of available dsp ip cores. resources available in the latticeecp2/m family table 2-9 shows the maximum number of multipliers for each member of the latticeecp2/m family. table 2-10 shows the maximum available ebr ram blocks in each latticeecp2/m device. ebr blocks, together with distrib- uted ram can be used to store variables locally for fast dsp operations. table 2-9. maximum number of dsp blocks in the latticeecp2/m family table 2-10. embedded sram in the latticeecp2/m family device dsp block 9x9 multiplier 18x18 multiplier 36x36 multiplier ecp2-6 3 24 12 3 ecp2-12 6 48 24 6 ecp2-20 7 56 28 7 ecp2-35 8 64 32 8 ecp2-50 18 144 72 18 ecp2-70 22 176 88 22 ecp2m20 6 48 24 6 ecp2m35 8 64 32 8 ecp2m50 22 176 88 22 ecp2m70 24 192 96 24 ecp2m100 42 336 168 42 device ebr sram block total ebr sram (kbits) ecp2-6 3 55 ecp2-12 12 221 ecp2-20 15 277 ecp2-35 18 332 ecp2-50 21 387 ecp2-70 60 1106 ecp2m20 66 1217 ecp2m35 114 2101 ecp2m50 225 4147 ecp2m70 246 4534 ecp2m100 288 5308
2-28 architecture lattice semiconductor latticeecp2/m family data sheet latticeecp2/m dsp performance table 2-11 lists the maximum performance in millions of mac operations per second (mmac) for each member of the latticeecp2/m family. table 2-11. dsp performance for further information on the sysdsp block, please see details of additional technical information at the end of this data sheet. programmable i/o cells (pic) each pic contains two pios connected to their respective sysio buffers as shown in figure 2-28. the pio block supplies the output data (do) and the tri-state control signal (to) to the sysio buffer and receives input from the buffer. table 2-14 provides the pio signal list. device dsp block dsp performance gmac ecp2-6 3 3.9 ecp2-12 6 7.8 ecp2-20 7 9.1 ecp2-35 8 10.4 ecp2-50 18 23.4 ecp2-70 22 28.6 ecp2m20 6 7.8 ecp2m35 8 10.4 ecp2m50 22 28.6 ecp2m70 24 31.2 ecp2m100 42 54.6
2-29 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-28. pic diagram two adjacent pios can be joined to provide a differential i/o pair (labeled as ? and ?? as shown in figure 2-28. the pad labels ? and ? distinguish the two pios. approximately 50% of the pio pairs on the left and right edges of the device can be con?ured as true lvds outputs. all i/o pairs can operate as inputs. opos1 o n eg1 td i n ck** i n dd i n ff ipos0 ipos1 clk ce lsr gsr n clk1 clk0 ceo cei sysio buffer pada ? pad b ? lsr gsr eclk1 ddrclkpol* *signals are a v aila b le on left/right/ b ottom edges only. ** selected b locks. iold0 di tristate re g ister block output re g ister block input re g ister block control muxes piob pioa opos0 opos2* o n eg0 o n eg2* dqsxfer* qpos1* q n eg1* q n eg0* qpos0* iolt0 eclk2
2-30 architecture lattice semiconductor latticeecp2/m family data sheet table 2-12. pio signal list pio the pio contains four blocks: an input register block, output register block, tristate register block and a control logic block. these blocks contain registers for operating in a variety of modes along with the necessary clock and selec- tion logic. input register block the input register blocks for pios in left, right and bottom edges contain delay elements and registers that can be used to condition high-speed interface signals, such as ddr memory interfaces and source synchronous inter- faces, before they are passed to the device core. figure 2-29 shows the diagram of the input register block for left, right and bottom edges. the input register block for the top edge contains one memory element to register the input signal as shown in figure 2-30. the following description applies to the input register block for pios in left, right and bottom edges of the device. input signals are fed from the sysio buffer to the input register block (as signal di). if desired, the input signal can bypass the register and delay elements and be used directly as a combinatorial signal (indd), a clock (inck) and, in selected blocks, the input to the dqs delay block. if an input delay is desired, designers can select either a ?ed delay or a dynamic delay del[3:0]. the delay, if selected, reduces input register hold time requirements when using a global clock. the input block allows three modes of operation. in the single data rate (sdr) the data is registered, by one of the registers in the single data rate sync register block, with the system clock. in ddr mode, two registers are used to sample the data on the positive and negative edges of the dqs signal, creating two data streams, d0 and d1. these two data streams are synchronized with the system clock before entering the core. further discussion on this topic is in the ddr memory section of this data sheet. name type description ce0, ce1 control from the core clock enables for input and output block ?p-?ps clk0, clk1 control from the core system clocks for input and output blocks eclk1, eclk2 control from the core fast edge clocks lsr control from the core local set/reset gsrn control from routing global set/reset (active low) inck 2 input to the core input to primary clock network or pll reference inputs dqs input to pio dqs signal from logic (routing) to pio indd input to the core unregistered data input to core inff input to the core registered input on positive edge of the clock (clk0) ipos0, ipos1 input to the core double data rate registered inputs to the core qpos0 1 , qpos1 1 input to the core gearbox pipelined inputs to the core qneg0 1 , qneg1 1 input to the core gearbox pipelined inputs to the core opos0, oneg0, opos2, oneg2 output data from the core output signals from the core for sdr and ddr operation opos1 oneg1 tristate control from the core signals to tristate register block for ddr operation del[3:0] control from the core dynamic input delay control bits td tristate control from the core tristate signal from the core used in sdr operation ddrclkpol control from clock polarity bus controls the polarity of the clock (clk0) that feed the ddr input block dqsxfer control from core controls signal to the output block 1. signals available on left/right/bottom only. 2. selected i/o.
2-31 architecture lattice semiconductor latticeecp2/m family data sheet by combining input blocks of the complementary pios and sharing some registers from output blocks, a gearbox function can be implemented, that takes a double data rate signal applied to pioa and converts it as four data streams, ipos0a, ipos1a, ipos0b and ipos1b. figure 2-29 shows the diagram using this gearbox function. for more information on this topic, please see information regarding additional documentation at the end of this data sheet. the signal ddrclkpol controls the polarity of the clock used in the synchronization registers. it ensures ade- quate timing when data is transferred from the dqs to system clock domain. for further discussion on this topic, see the ddr memory section of this data sheet. figure 2-29. input register block for left, right and bottom edges clock transfer re g isters clock transfer re g isters sdr & sync re g isters d1 d2 d0 ddr re g isters d q d-type d q d-type d q d-type d q d-type /latch d q d-type 0 1 d q d q 0 1 fixed delay dynamic delay di (from sysio b u ffer) di (from sysio b u ffer) i n ck** i n dd ipos0a qpos0a ipos1a qpos1a del [3:0] clk0 (of pio a) delayed dqs 0 1 clka dq d q d q 0 1 0 1 d q d q 0 1 d q d q 0 1 fixed delay dynamic delay i n ck** i n dd ipos0b qpos0b ipos1b qpos1b del [3:0] clk0 (of pio b) delayed dqs clkb /latch true pio (a) in lvds i/o pair comp pio (b) in lvds i/o pair d-type* d-type* d-type /latch d-type /latch d-type* d-type* from routin g to routin g d1 d2 d0 ddr re g isters sdr & sync re g isters 0 1 ddrsrc gear b ox config u ration bit ddrclkpol ddrclkpol *shared w ith o u tp u t register **selected pio. n ote: simplified v ersion does not sho w ce and set/reset details from routin g to routin g to dqs delay block** to dqs delay block** d-type d-type d-type
2-32 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-30. input register block top edge output register block the output register block provides the ability to register signals from the core of the device before they are passed to the sysio buffers. the blocks on the pios on the left, right and bottom contains a register for sdr operation that is combined with an additional latch for ddr operation. figure 2-31 shows the diagram of the output register block for pios on the left, right and the bottom edges. figure 2-32 shows the diagram of the output register block for pios on the top edge of the device. in sdr mode, oneg0 feeds one of the ?p-?ps that then feeds the output. the ?p-?p can be con?ured as a d- type or latch. in ddr mode, oneg0 and opos0 are fed into registers is fed into registers on the positive edge of the clock. then at the next clock cycle this registered opos0 is latched. a multiplexer running off the same clock selects the correct register for feeding to the output (d0). by combining output blocks of the complementary pios and sharing some registers from input blocks, a gearbox function can be implemented, that takes four data streams oneg0a, oneg1a, oneg1b and oneg1b. figure 2- 32 shows the diagram using this gearbox function. for more information on this topic, please see information regarding additional documentation at the end of this data sheet. fixed delay dynamic delay n ote: simplified v ersion does not sho w ce and set/reset details. *on selected b locks. to routin g di (from sysio bu ffer) clk0 (from ro u ting) del[3:0] i n ck* i n dd d-type ipos0 /latch dq
2-33 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-31. output and tristate block for left, right and bottom edges clock transfer registers o n eg1 clka to opos1 from routin g td dq dq dq 0 1 0 1 0 1 dq dq dq 0 1 0 1 d q d-type * d q latch d q 0 1 0 1 0 1 0 1 o n eg0 opos0 do programma b le control programma b le control 0 1 eclk1 eclk2 clk1 tristate lo g ic tristate lo g ic output lo g ic true pio (a) in lvds i/o pair t o sy s io b uff e r o n eg1 clkb to opos1 from routin g td d q d q d q 0 1 0 1 0 1 d q d-type /latch d-type /latch d-type /latch d-type /latch dq dq 0 1 0 1 d q dq latch d-type d-type latch latch d-type latch d-type latch dq o n eg0 opos0 do eclk1 eclk2 clk1 output lo g ic t o s ys io buf fe r comp pio (b) in lvds i/o pair (clkb) (clka) d-type * d-type* d-type* clock transfer re g isters ddr output re g isters ddr output re g isters * shared w ith inp u t register n ote: simplified v ersion does not sho w ce and set/reset details 0 1 dqsxfer dqsxfer 0 1 0 1
2-34 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-32. output and tristate block, top edge tristate register block the tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysio buffers. the block contains a register for sdr operation and an additional latch for ddr operation. figure 2-31 shows the diagram of the tristate register block with the output block for the left, right and bottom edges and figure 2-32 shows the diagram of the tristate register block with the output block for the top edge. in sdr mode, oneg1 feeds one of the ?p-?ps that then feeds the output. the ?p-?p can be con?ured a d- type or latch. in ddr mode, oneg1 and opos1 are fed into registers on the positive edge of the clock. then in the next clock the registered opos1 is latched. a multiplexer running off the same clock cycle selects the correct register for feeding to the output (d0). control logic block the control logic block allows the selection and modi?ation of control signals for use in the pio block. a clock is selected from one of the clock signals provided from the general purpose routing, one of the edge clocks (eclk1/ eclk2) and a dqs signal provided from the programmable dqs pin and provided to the input register block. the clock can optionally be inverted. ddr memory support certain pics have additional circuitry to allow the implementation of high speed source synchronous and ddr memory interfaces. the support varies by edge of the device as detailed below. left and right edges pics on these edges have registered elements that support ddr memory interfaces. one of every 16 pios con- tains a delay element to facilitate the generation of dqs signals. the dqs signal feeds the dqs bus which spans the set of 16 pios. figure 2-33 shows the assignment of dqs pins in each set of 16 pios. bottom edge pics on these edges have registered elements that support ddr memory interfaces. one of every 18 pios con- tains a delay element to facilitate the generation of dqs signals. the dqs signal feeds the dqs bus that spans the set of 18 pios. figure 2-34 shows the assignment of dqs pins in each set of 18 pios. to o n eg1 n ote: simplified v ersion does not sho w ce and set/reset details. from routin g td d q d-type 0 1 0 1 d q d-type /latch 0 1 o n eg0 do eclk1 eclk2 clk1 tristate lo g ic output lo g ic to sys io buffer (clka) 0 1 /latch
2-35 architecture lattice semiconductor latticeecp2/m family data sheet top edge the pics on the top edge are different from pios on the left, right and bottom edges. pios on this edge do not have registers or dqs signals. the exact dqs pins are shown in a dual function in the logic signal connections table in this data sheet. addi- tional detail is provided in the signal descriptions table. the dqs signal from the bus is used to strobe the ddr data from the memory into input register blocks. interfaces on the left and right edges are designed for ddr mem- ories that support 16 bits of data, whereas interfaces on the bottom are designed for memories that support 18 bits of data. figure 2-33. dqs input routing for the left and right edges of the device pio b pio a pio b pio a assi g ned dqs pin dqs delay sysio b u ffer pada "t" padb "c" l v ds pair pada "t" padb "c" l v ds pair pio a pio b pada "t" padb "c" l v ds pair pio a pio b pada "t" padb "c" l v ds pair pio a pio b pada "t" padb "c" l v ds pair pio a pio b pada "t" padb "c" l v ds pair pio a pio b pada "t" padb "c" l v ds pair pio a pio b pada "t" padb "c" l v ds pair
2-36 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-34. dqs input routing for the bottom edge of the device dll calibrated dqs delay block source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. for most interfaces a pll is used for this adjustment. however in ddr memories the clock (referred to as dqs) is not free-running so this approach cannot be used. the dqs delay block provides the required clock alignment for ddr memory interfaces. the dqs signal (selected pios only, as shown in figure 2-35) feeds from the pad through a dqs delay element to a dedicated dqs routing resource. the dqs signal also feeds polarity control logic which controls the polarity of the clock to the sync registers in the input register blocks. figure 2-35 and figure 2-36 show how the dqs transi- tion signals are routed to the pios. the temperature, voltage and process variations of the dqs delay block are compensated by a set of calibration (6-bit bus) signals from two dedicated dlls (ddr_dll) on opposite sides of the device. each dll compensates dqs delays in its half of the device as shown in figure 2-35. the dll loop is compensated for temperature, volt- age and process variations by the system clock and feedback loop. pio b pio a pio b pio a assi g ned dqs pin dqs delay sysio b u ffer pada "t" padb "c" l v ds pair pada "t" padb "c" l v ds pair pio a pio b pada "t" padb "c" l v ds pair pio a pio b pada "t" padb "c" l v ds pair pio a pio b pada "t" padb "c" l v ds pair pio a pio b pada "t" padb "c" l v ds pair pio a pio b pada "t" padb "c" l v ds pair pio b pio a pada "t" padb "c" l v ds pair pio a pio b pada "t" padb "c" l v ds pair
2-37 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-35. edge clock, dll calibration and dqs local bus distribution i/o bank 5 n ote: bank 8 is not sho w n. i/o bank 4 i/o b a n k 6 i/o b a n k 3 i/o b a n k 2 i/o bank 0 i/o bank 1 ddr_dll (right) i/o b a n k 7 ddr_dll (left) eclk1 eclk2 delayed dqs polarity control dqsxfer dqs delay control bus dqs input spans 1 8 pios spans 16 pios
2-38 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-36. dqs local bus polarity control logic in a typical ddr memory interface design, the phase relationship between the incoming delayed dqs strobe and the internal system clock (during the read cycle) is unknown. the latticeecp2/m family contains dedicated circuits to transfer data between these domains. to prevent set-up and hold violations, at the domain transfer between dqs (delayed) and the system clock, a clock polarity selector is used. this changes the edge on which the data is registered in the synchronizing registers in the input register block. this requires evaluation at the start of each read cycle for the correct clock polarity. prior to the read operation in ddr memories, dqs is in tristate (pulled by termination). the ddr memory device drives dqs low at the start of the preamble state. a dedicated circuit detects the ?st dqs rising edge after the pre- amble state. this signal is used to control the polarity of the clock to the synchronizing registers. sysio buffer ddr datain pad di clk1 cei pio sysio buffer gsr dqs to sync reg. dqs to ddr reg. dqs stro b e pad pio dqsdel polarity control lo g ic dqs cali b ration bu s from dll dqsxfer output re g ister block input re g ister block dqsxfer dc n tl[6:0] polarit y control dqs di dqsxferdel* dqsxfer dc n tl[6:0] *dqsxferdel shifts eclk1 b y 90 % and is not associated w ith a partic u lar pio. dc n tl[6:0] eclk1 clk1 eclk2 eclk1
2-39 architecture lattice semiconductor latticeecp2/m family data sheet dqsxfer latticeecp2/m devices provide a dqsxfer signal to the output buffer to assist it in data transfer to ddr memo- ries that require dqs strobe be shifted 90 o . this shifted dqs strobe is generated by the dqsdel block. the dqsxfer signal runs the span of the data bus. sysio buffer each i/o is associated with a ?xible buffer referred to as a sysio buffer. these buffers are arranged around the periphery of the device in groups referred to as banks. the sysio buffers allow users to implement the wide variety of standards that are found in todays systems including lvcmos, sstl, hstl, lvds and lvpecl. sysio buffer banks latticeecp2/m devices have nine sysio buffer banks: eight banks for user i/os arranged two per side. the ninth sysio buffer bank (bank 8) is located adjacent to bank 3 and has dedicated/shared i/os for con?uration. w hen a shared pin is not used for con?uration it is available as a user i/o. each bank is capable of supporting multiple i/o standards. each sysio bank has its own i/o supply voltage (v ccio ). in addition, each bank, except bank 8, has voltage references, v ref1 and v ref2 , that allow it to be completely independent from the others. bank 8 shares two voltage references, v ref1 and v ref2 , with bank 3. figure 2-37 shows the nine banks and their associated sup- plies. in latticeecp2/m devices, single-ended output buffers and ratioed input buffers (lvttl, lvcmos and pci) are powered using v ccio . lvttl, lvcmos33, lvcmos25 and lvcmos12 can also be set as ?ed threshold inputs independent of v ccio . each bank can support up to two separate v ref voltages, v ref1 and v ref2 , that set the threshold for the refer- enced input buffers. some dedicated i/o pins in a bank can be con?ured to be a reference voltage supply pin. each i/o is individually con?urable based on the banks supply and reference voltages.
2-40 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-37. latticeecp2 banks v ref1(2) gnd bank 2 v ccio2 v ref2(2) v ref1(3) gnd bank 3 v ccio3 v ref2(3) v ref1(7) gnd bank 7 v ccio7 v ref2(7) v ref1(6) gnd bank 6 v ccio6 v ref2(6) bank 5 bank 4 v ref1(0) gnd bank 0 v ccio0 v ref2(0) v ref1(1) gnd bank 1 v ccio1 v ref2(1) gnd bank 8 v ccio8 left right top v ref1(5) gnd v ccio5 v ref2(5) v ref1(4) gnd v ccio4 v ref2(4) bottom
2-41 architecture lattice semiconductor latticeecp2/m family data sheet figure 2-38. latticeecp2m banks latticeecp2/m devices contain two types of sysio buffer pairs. 1. top (bank 0 and bank 1) sysio buffer pairs (single-ended outputs only) the sysio buffer pairs in the top banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). one of the referenced input buffers can also be con- ?ured as a differential input. the two pads in the pair are described as ?rue and ?omp? where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. 2. bottom (bank 4 and bank 5) sysio buffer pairs (single-ended outputs only) the sysio buffer pairs in the bottom banks of the device consist of two single-ended output drivers and two v ref1(5) gnd v ccio5 v ref2(5) v ref1(4) gnd v ccio4 v ref2(4) v ref1(0) gnd v ccio0 v ref2(0) v ref1(1) gnd v ccio1 v ref2(1) v ref1(7) gnd v ccio7 v ref2(7) v ref1(6) gnd v ccio6 v ref2(6) v ref1(2) gnd v ccio2 v ref2(2) v ref1(3) gnd v ccio3 v ref2(3) gnd v ccio8 right bank 2 bank 3 bank 7 bank 6 bank 5 bank 4 bank 0 bank 1 bank 8 bottom serdes quad serdes quad serdes quad serdes quad left top
2-42 architecture lattice semiconductor latticeecp2/m family data sheet sets of single-ended input buffers (both ratioed and referenced). one of the referenced input buffers can also be con?ured as a differential input. the two pads in the pair are described as ?rue and ?omp? where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. 3. left and right (banks 2, 3, 6 and 7) sysio buffer pairs (50 % differential and 100 % single-ended outputs) the sysio buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. one of the ref- erenced input buffers can also be con?ured as a differential input. in these banks the two pads in the pair are described as ?rue and ?omp? where the true pad is associated with the positive side of the differential i/o, and the comp (complementary) pad is associated with the negative side of the differential i/o. lvds differential output drivers are available on 50% of the buffer pairs on the left and right banks. 4. bank 8 sysio buffer pairs (single-ended outputs, only on shared pins when not used by con?ura- tion) the sysio buffers in bank 8 consist of single-ended output drivers and single-ended input buffers (both ratioed and referenced). the referenced input buffer can also be con?ured as a differential input. the two pads in the pair are described as ?rue and ?omp? where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. in latticeecp2 devices, only the i/os on the bottom banks have programmable pci clamps. in latticeecp2m devices, the i/os on the left and bottom banks have programmable pci clamps. typical sysio i/o behavior during power-up the internal power-on-reset (por) signal is deactivated when v cc , v ccio8 and v ccaux have reached satisfactory levels. after the por signal is deactivated, the fpga core logic becomes active. it is the users responsibility to ensure that all other v ccio banks are active with valid input logic levels to properly control the output logic states of all the i/o banks that are critical to the application. for more information on controlling the output logic state with valid input logic levels during power-up in latticeecp2/m devices, see details of additional technical documentation at the end of this data sheet. the v cc and v ccaux supply the power to the fpga core fabric, whereas the v ccio supplies power to the i/o buff- ers. in order to simplify system design while providing consistent and predictable i/o behavior, it is recommended that the i/o buffers be powered-up prior to the fpga core fabric. v ccio supplies should be powered-up before or together with the v cc and v ccaux supplies. supported sysio standards the latticeecp2/m sysio buffer supports both single-ended and differential standards. single-ended standards can be further subdivided into lvcmos, lvttl and other standards. the buffers support the lvttl, lvcmos 1.2v, 1.5v, 1.8v, 2.5v and 3.3v standards. in the lvcmos and lvttl modes, the buffer has individual con?ura- tion options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. other single-ended standards supported include sstl and hstl. differential standards supported include lvds, mlvds, blvds, lvpecl, rsds, differential sstl and differential hstl. tables 2-13 and 2-14 show the i/ o standards (together with their supply and reference voltages) supported by latticeecp2/m devices. for further information on utilizing the sysio buffer to support a variety of standards please see the details of additional techni- cal information at the end of this data sheet.
2-43 architecture lattice semiconductor latticeecp2/m family data sheet table 2-13. supported input standards input standard v ref (nom.) v ccio 1 (nom.) single ended interfaces lvttl lvcmos33 lvcmos25 lvcmos18 1.8 lvcmos15 1.5 lvcmos12 pci 33 3.3 hstl18 class i, ii 0.9 hstl15 class i 0.75 sstl3 class i, ii 1.5 sstl2 class i, ii 1.25 sstl18 class i, ii 0.9 differential interfaces differential sstl18 class i, ii differential sstl2 class i, ii differential sstl3 class i, ii differential hstl15 class i differential hstl18 class i, ii lvds, mlvds, lvpecl, blvds, rsds 1 w hen not speci?d, v ccio can be set anywhere in the valid operating range (page 3-1).
2-44 architecture lattice semiconductor latticeecp2/m family data sheet table 2-14. supported output standards hot socketing latticeecp2/m devices have been carefully designed to ensure predictable behavior during power-up and power- down. during power-up and power-down sequences, the i/os remain in tri-state until the power supply voltage is high enough to ensure reliable operation. in addition, leakage into i/o pins is controlled to within speci?d limits. this allows for easy integration with the rest of the system. these capabilities make the latticeecp2/m ideal for many multiple power supply and hot-swap applications. output standard drive v ccio (nom.) single-ended interfaces lvttl 4ma, 8ma, 12ma, 16ma, 20ma 3.3 lvcmos33 4ma, 8ma, 12ma 16ma, 20ma 3.3 lvcmos25 4ma, 8ma, 12ma, 16ma, 20ma 2.5 lvcmos18 4ma, 8ma, 12ma, 16ma 1.8 lvcmos15 4ma, 8ma 1.5 lvcmos12 2ma, 6ma 1.2 lvcmos33, open drain 4ma, 8ma, 12ma 16ma, 20ma lvcmos25, open drain 4ma, 8ma, 12ma 16ma, 20ma lvcmos18, open drain 4ma, 8ma, 12ma 16ma lvcmos15, open drain 4ma, 8ma lvcmos12, open drain 2ma, 6ma pci33 n/a 3.3 hstl18 class i, ii n/a 1.8 hstl15 class i n/a 1.5 sstl3 class i, ii n/a 3.3 sstl2 class i, ii n/a 2.5 sstl18 class i, ii n/a 1.8 differential interfaces differential sstl3, class i, ii n/a 3.3 differential sstl2, class i, ii n/a 2.5 differential sstl18, class i, ii n/a 1.8 differential hstl18, class i, ii n/a 1.8 differential hstl15, class i n/a 1.5 lvds n/a 2.5 mlvds 1 n/a 2.5 blvds 1 n/a 2.5 lvpecl 1 n/a 3.3 rsds 1 n/a 2.5 1. emulated with external resistors. for more detail, please see information regarding additional technical documentation at the end of this data sheet.
2-45 architecture lattice semiconductor latticeecp2/m family data sheet serdes and pcs (physical coding sublayer) latticeecp2m devices feature up to 16 channels of embedded serdes arranged in quads at the corners of the devices. figure 2-39 shows the position of the quad blocks in relation to the pfu array for latticeecp2m70 and latticeecp2m100 devices. table 2-15 shows the location of quads for all the devices. each quad contains, four dedicated serdes (ch0 to ch3) for high-speed, full-duplex serial data transfer. each quad also has pcs block that interfaces to the serdes channels and contain digital logic to support an array of popular data protocols. pcs also contain logic to interface to fpga core. figure 2-39. serdes quads (latticeecp2m70/latticeecp2m100) table 2-15. available serdes quads per latticeecp2m devices serdes block a differential receiver receives the serial encoded data stream, equalizes the signal, extracts the buried clock and de-serializes the data-stream before passing the 8- or 10-bit data to the pcs logic. the transmit channel receives the parallel (8- or 10-bit) encoded data, serializes the data and transmits the serial bit stream through the differen- tial buffers. there is a single transmit clock per quad. figure 2-40 shows a single channel serdes and its inter- face to the pcs logic. each serdes receiver channel provides a recovered clock to the pcs block and to the fpga core logic. device urc quad ulc quad lrc quad llc quad ecp2m20 available ecp2m35 available ecp2m50 available available ecp2m70 available available available available ecp2m100 available available available available ulc serdes quad urc serdes quad lrc serdes quad llc serdes quad ch 3 pcs digital logic ch 2 ch 1 ch 0 ch 3 pcs digital logic ch 2 ch 1 ch 0 ch 3 pcs digital logic ch 2 ch 1 ch 0 ch 3 pcs digital logic ch 2 ch 1 ch 0
2-46 architecture lattice semiconductor latticeecp2/m family data sheet each transmit and receive channel has its independent power supplies. the output and input buffers of each channel have their own independent power supplies too. in addition, there are separate power supplies for pll, terminating resistor per quad. figure 2-40. simpli?d channel block diagram for serdes and pcs pcs as shown in figure 2-40, the pcs receives the parallel digital data from the deserializer receivers and adjusts the polarity, detects, byte boundary, decodes (8b/10b) and provides clock tolerance compensation (ctc) fifo for changing the clock domain from receiver clock to the fpga clock. for the transmit channel, the pcs block receives the parallel data from the fpga core, encodes it with 8b/10b, adjusts the polarity and passes the 8/10 bit data to the transmit serdes channel. the pcs also provides bypass modes that allow a direct 8-bit or 10-bit interface from the serdes to the fpga logic. the pcs interface to fpga can also be programmed to run at 1/2 speed for a 16-bit or 20-bit interface to the fpga logic. sci (serdes client interface) bus the serdes client interface (sci) is a soft ip interface that allow the serdes/pcs quad block to be controlled by registers as opposed to the con?uration memory cells. it is a simple register con?uration interface. the isplever design tools from lattice support all modes of the pcs. most modes are dedicated to applications associated with a speci? industry standard data protocol. other more general purpose modes allow users to de?e their own operation. w ith isplever, the user can de?e the mode for each quad in a design. popular standards such as 10gb ethernet and x4 pci-express and 4x serial rapidio can be implemented using ip (provided by lattice), a single quad (four serdes channels and pcs) and some additional logic from the core. for further information on serdes, please see details of additional technical documentation at the end of this data sheet. deserializer 1: 8 /1:10 polarity adjust equalizer byte boundary detect, 8 b/10b decoder ctc fifo down sample fifo up sample fifo 8 b/10b encoder polarity adjust serializer tx pll fpga transmit clock recovered clock rx refclk fpga receive clock to fpga core transmit receiver 8 /10 bits or 16/20 bits transmit data elastic buffer read clock 16/20 bits receive data from transmit pll (in common block) serdes (analo g ) pcs (di g ital) 8 :1/10:1 tx refclk
2-47 architecture lattice semiconductor latticeecp2/m family data sheet ieee 1149.1-compliant boundary scan testability all latticeecp2/m devices have boundary scan cells that are accessed through an ieee 1149.1 compliant test access port (tap). this allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for veri?ation. the test access port consists of dedicated i/os: tdi, tdo, tck and tms. the test access port has its own supply voltage v ccj and can operate with lvcmos3.3, 2.5, 1.8, 1.5 and 1.2 standards. for more details on boundary scan test, please see information regarding additional technical documentation at the end of this data sheet. device con?uration all latticeecp2/m devices contain two ports that can be used for device con?uration. the test access port (tap), which supports bit-wide con?uration, and the sysconfig port, support both byte-wide and serial con?uration, including the standard spi flash interface. the tap supports both the ieee standard 1149.1 boundary scan speci?ation and the ieee standard 1532 in- system con?uration speci?ation. the sysconfig port is a 20-pin interface with six i/os used as dedicated pins with the remainder used as dual-use pins. see lattice technical note number tn1108, latticeecp2 sysconfig usage guide for more information on using the dual-use pins as gen- eral purpose i/os. on power-up, the fpga sram is ready to be con?ured using the selected sysconfig port. once a con?uration port is selected, it will remain active throughout that con?uration cycle. the ieee 1149.1 port can be activated any time after power-up by sending the appropriate command through the tap port. enhanced con?uration option latticeecp2/m devices have enhanced con?uration features such as: decryption support, transfr i/o and dual boot image support. 1. decryption support latticeecp2/m devices provide on-chip, one time programmable (otp) non-volatile key storage to support decryption of a 128-bit aes encrypted bitstream, securing designs and deterring design piracy. 2. transfr (transparent field recon?uration) transfr i/o (tfr) is a unique lattice technology that allows users to update their logic in the ?ld without interrupting system operation using a single ispvm command. transfr i/o allows i/o states to be frozen dur- ing device con?uration. this allows the device to be ?ld updated with a minimum of system disruption and downtime. see lattice technical note number tn1087, minimizing system interruption during con?uration using transfr technology, for details. 3. dual boot image support dual boot images are supported for applications requiring reliable remote updates of con?uration data for the system fpga. after the system is running with a basic con?uration, a new boot image can be downloaded remotely and stored in a separate location in the con?uration storage device. any time after the update the latticeecp2/m can be re-booted from this new con?uration ?e. if there is a problem such as corrupt data dur- ing download or incorrect version number with this new boot image, the latticeecp2/m device can revert back to the original backup con?uration and try again. this all can be done without power cycling the system. for more information on device con?uration, please see details of additional technical documentation at the end of this data sheet. software error detect (sed) support latticeecp2/m devices have dedicated logic to perform crc checks. during con?uration, the con?uration data bitstream can be checked with crc logic block. in addition the latticeecp2 device can also be programmed for
2-48 architecture lattice semiconductor latticeecp2/m family data sheet checking soft errors (sed) in sram. this sed operation can be run in the background during user mode. if a soft error occurs, during user mode (normal operation) the device can be programmed to either reload from a known good boot image or generate an error signal. for further information on soft error detect (sed) support, please see details of additional technical documenta- tion at the end of this data sheet. external resistor latticeecp2/m devices require a single external, 10k ohm ?% value between the xres pin and ground. device con?uration will not be completed if this resistor is missing. there is no boundary scan register on the external resistor pad. on-chip oscillator every latticeecp2/m device has an internal cmos oscillator which is used to derive a master clock for con?ura- tion. the oscillator and the master clock run continuously and are available to user logic after con?uration is com- pleted. the software default value of the master clock is 2.5mhz. table 2-16 lists all the available master clock frequencies. w hen a different master clock is selected during the design process, the following sequence takes place: 1. device powers up with a master clock frequency of 3.1mhz. 2. during con?uration, users select a different master clock frequency. 3. the master clock frequency changes to the selected frequency once the clock con?uration bits are received. 4. if the user does not select a master clock frequency, then the con?uration bitstream defaults to the master clock frequency of 2.5mhz. this internal cmos oscillator is available to the user by routing it as an input clock to the clock tree. for further information on the use of this oscillator for con?uration or user mode, please see details of additional technical documentation at the end of this data sheet. table 2-16. selectable master clock (cclk) frequencies during con?uration density shifting the latticeecp2/m family is designed to ensure that different density devices in the same family and in the same package have the same pinout. furthermore, the architecture ensures a high success rate when performing design migration from lower density devices to higher density devices. in many cases, it is also possible to shift a lower uti- lization design targeted for a high-density device to a lower density device. however, the exact details of the ?al resource utilization will impact the likely success in each case. design migration between latticeecp2 and latticeecp2m families is not possible. cclk (mhz) cclk (mhz) cclk (mhz) 2.5 1 ?5 ?551 5.4 20 55 ?660 ?0 ?4 10.0 41 1. software default frequency.
www.latticesemi.com 3-1 ds1006 dc and switching_01.5 july 2007 advance data sheet ds1006 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. recommended operating conditions absolute maximum ratings 1, 2, 3 1. stress above those listed under the ?bsolute maximum ratings may cause permanent damage to the device. functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. 2. compliance with the lattice thermal management document is required. 3. all voltages referenced to gnd. supply voltage v cc . . . . . . . . . . . . . . . . . . . -0.5 to 1.32v supply voltage v ccaux . . . . . . . . . . . . . . . . -0.5 to 3.75v supply voltage v ccj . . . . . . . . . . . . . . . . . . -0.5 to 3.75v output supply voltage v ccio . . . . . . . . . . . -0.5 to 3.75v input or i/o tristate voltage applied 4 . . . . . . -0.5 to 3.75v storage temperature (ambient) . . . . . . . . . -65 to 150? junction temperature (tj) . . . . . . . . . . . . . . . . . . +125? 4. overshoot and undershoot of -2v to (v ihmax + 2) volts is permitted for a duration of <20ns. symbol parameter min. max. units v cc 1, 4, 5 core supply voltage 1.14 1.26 v v ccaux 1, 3, 4, 5 auxiliary supply voltage 3.135 3.465 v v ccpll pll supply voltage 1.14 1.26 v v ccio 1, 2, 4 i/o driver supply voltage 1.14 3.465 v v ccj 1 supply voltage for ieee 1149.1 test access port 1.14 3.465 v t jcom junction temperature, commercial operation 0 85 c t jind junction temperature, industrial operation -40 100 ? serdes external power supply (for latticeecp2m family only) v ccib input buffer power supply (1.2v) 1.14 1.26 v input buffer power supply (1.5v) 1.425 1.575 v v ccob output buffer power supply (1.2v) 1.14 1.26 v output buffer power supply (1.5v) 1.425 1.575 v v ccaux33 termination resistor switching power supply 3.135 3.465 v v ccrx 6 receive power supply 1.14 1.26 v v cctx 6 transmit power supply 1.14 1.26 v v ccp 6 pll and reference clock buffer power 1.14 1.26 v 1. if v ccio or v ccj is set to 1.2v, they must be connected to the same power supply as v cc. if v ccio or v ccj is set to 3.3v, they must be con- nected to the same power supply as v ccaux . v cc and v ccpll must be connected to the same power supply. 2. see recommended voltages by i/o standard in subsequent table. 3. v ccaux ramp rate must not exceed 30mv/? during power-up when transitioning between 0v and 3.3v. 4. for proper power-up con?uration, users must ensure that the con?uration control signals such as the cfgx, initn, programn a nd done pins are driven to the proper logic levels when the device powers up. the device power-up is triggered by the last of v cc , v ccaux or v ccio8 supplies that reaches its minimum valid levels. alternatively, if the con?uration control signals are pulled up by v ccio8 , the v ccio8 (con?uration i/o bank) voltage must be powered up prior to or at the same time as the last of vcc or vccaux reaches its minimu m levels. 5. for power-up, v cc must reach its valid minimum value before powering up v ccaux (latticeecp2/m ? version devices only). 6. v ccrx ,v cctx and v ccp must be tied together in each quad and all quads need to be powered up. latticeecp2/m family data sheet dc and switching characteristics
3-2 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet hot socketing speci?ations 1, 2, 3, 4 symbol parameter condition min. typ. max. units i dk input or i/o leakage current 0 v in v ih (max.) +/-1000 ? i hdin 5 serdes average input current when device is powered down and inputs are driven 4ma 1. v cc , v ccaux and v ccio should rise/fall monotonically. v cc and v ccpll must be connected to the same power supply (applies to ecp2-6, ecp2-12 and ecp2-20 only). 2. 0 v cc v cc (max), 0 v ccio v ccio (max) or 0 v ccaux v ccaux (max). 3. i dk is additive to i pu , i p w or i bh . 4. lvcmos and lvttl only. 5. assumes that the device is powered down with all supplies grounded, both p and n inputs driven by a cml driver with maximum a llowed v ccib of 1.575v, 8b10b data and internal ac coupling.
3-3 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet dc electrical characteristics over recommended operating conditions symbol parameter condition min. typ. max. units i il , i ih 1 input or i/o low leakage 0 v in (v ccio - 0.2v) 10 ? i ih 1 input or i/o high leakage (v ccio - 0.2v) < v in 3.6v 150 ? i pu i/o active pull-up current 0 v in 0.7 v ccio -30 -210 ? i pd i/o active pull-down current v il (max) v in v ih (max) 30 210 ? i bhls bus hold low sustaining current v in = v il (max) 30 ? i bhhs bus hold high sustaining current v in = 0.7 v ccio -30 ? i bhlo bus hold low overdrive current 0 v in v ccio 210 ? i bhho bus hold high overdrive current 0 v in v ccio -210 ? v bht bus hold trip points 0 v in v ih (max) v il (max) v ih (min) v c1 i/o capacitance 2 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?pf c2 dedicated input capacitance 2 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?pf 1. input or i/o leakage current is measured with the pin con?ured as an input or as an i/o with the output driver tri-stated. i t is not measured with the output driver active. bus maintenance circuits are disabled. 2. t a 25 o c, f = 1.0mhz.
3-4 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet latticeecp2 supply current (standby) 1, 2, 3, 4 over recommended operating conditions symbol parameter device typ. 5 units i cc core power supply current ecp2-6 14 ma ecp2-12 23 ma ecp2-20 35 ma ecp2-35 44 ma ecp2-50 64 ma ecp2-70 91 ma i ccaux auxiliary power supply current ecp2-6 24 ma ecp2-12 24 ma ecp2-20 24 ma ecp2-35 24 ma ecp2-50 24 ma ecp2-70 24 ma i ccgpll gpll power supply current (per gpll) ecp2-35, -50, -70 only 0.5 ma i ccspll gpll power supply current (per spll) ecp2-35, -50, -70 only 0.5 ma i ccio bank power supply current (per bank) ecp2-6 1 ma ecp2-12 2 ma ecp2-20 3 ma ecp2-35 3 ma ecp2-50 4 ma ecp2-70 5 ma i ccj vccj power supply current all devices 3 ma 1. for further information on supply current, please see details of additional technical documentation at the end of this data sheet. 2. assumes all outputs are tristated, all inputs are con?ured as lvcmos and held at the v ccio or gnd. 3. frequency 0mhz. 4. pattern represents a ?lank con?uration data ?e. 5. t j = 25?, power supplies at normal voltage.
3-5 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet latticeecp2m supply current (standby) 1, 2, 3, 4 over recommended operating conditions symbol parameter device typ. 5 units i cc core power supply current ecp2m20 39 ma ecp2m35 61 ma ecp2m50 ma ecp2m70 ma ecp2m100 ma i ccaux auxiliary power supply current ecp2m20 24 ma ecp2m35 24 ma ecp2m50 ma ecp2m70 ma ecp2m100 ma i ccgpll gpll power supply current (per gpll) all devices 0.5 ma i ccspll gpll power supply current (per spll) all devices 0.5 ma i ccio bank power supply current (per bank) ecp2m20 2 ma ecp2m35 3 ma ecp2m50 ma ecp2m70 ma ecp2m100 ma i ccj vccj power supply current all devices 3 ma 1. for further information on supply current, please see details of additional technical documentation at the end of this data sheet. 2. assumes all outputs are tristated, all inputs are con?ured as lvcmos and held at the v ccio or gnd. 3. frequency 0mhz. 4. pattern represents a ?lank con?uration data ?e. 5. t j = 25?, power supplies at normal voltage.
3-6 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet latticeecp2 initialization supply current 1, 2, 3, 4 over recommended operating conditions symbol parameter device typ. 5, 6 units i cc core power supply current ecp2-6 34 ma ecp2-12 54 ma ecp2-20 82 ma ecp2-35 135 ma ecp2-50 187 ma ecp2-70 267 ma i ccaux auxiliary power supply current ecp2-6 30 ma ecp2-12 30 ma ecp2-20 30 ma ecp2-35 30 ma ecp2-50 30 ma ecp2-70 30 ma i ccgpll gpll power supply current (per gpll) ecp2-35, -50, -70 only 0.5 ma i ccspll spll power supply current (per spll) ecp2-35, -50, -70 only 0.5 ma i ccio bank power supply current (per bank) all devices 3 ma i ccj vccj power supply current all devices 4 ma 1. until done signal is active. 2. for further information on supply current, please see details of additional technical documentation at the end of this data s heet. 3. assumes all outputs are tristated, all inputs are con?ured as lvcmos and held at the v ccio or gnd. 4. frequency 0mhz. 5. t j = 25 o c, power supplies at nominal voltage. 6. a speci? con?uration pattern is used that scales with the size of the device; consists of 75% pfu utilization, 50% ebr, and 25% i/o con- ?uration.
3-7 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet latticeecp2m initialization supply current 1, 2, 3, 4 over recommended operating conditions symbol parameter device typ. 5, 6 units i cc core power supply current ecp2m20 41 ma ecp2m35 107 ma ecp2m50 169 ma ecp2m70 254 ma ecp2m100 378 ma i ccaux auxiliary power supply current ecp2m20 30 ma ecp2m35 30 ma ecp2m50 30 ma ecp2m70 30 ma ecp2m100 30 ma i ccgpll gpll power supply current (per gpll) all devices 0.5 ma i ccspll spll power supply current (per spll) all devices 0.5 ma i ccio bank power supply current (per bank) all devices 3 ma i ccj vccj power supply current all devices 4 ma 1. until done signal is active. 2. for further information on supply current, please see details of additional technical documentation at the end of this data s heet. 3. assumes all outputs are tristated, all inputs are con?ured as lvcmos and held at the v ccio or gnd. 4. frequency 0mhz. 5. t j = 25 o c, power supplies at nominal voltage. 6. a speci? con?uration pattern is used that scales with the size of the device; consists of 75% pfu utilization, 50% ebr, and 25% i/o con- ?uration.
3-8 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet serdes power supply re q uirements (latticeecp2m family only) 1 over recommended operating conditions serdes power (latticeecp2m family only) table 3-1 presents the serdes power for one channel. table 3-1. serdes power 1 symbol description typ. 2 units standby (power down) i cctx-sb v cctx current (per channel) 10 ? i ccrx-sb v ccrx current (per channel) 75 ? i ccib-sb input buffer current (per channel) 0 a i ccob-sb output buffer current (per channel) 0 a i ccp-sb serdes pll current (per quad) 30 ? i ccax33-sb serdes termination current (per quad) 10 ? operating (data rate = 3.125 gbps) i cctx-op v cctx current (per channel) 19 ma i ccrx-op v ccrx current (per channel) 34 ma i ccib-op input buffer current (per channel) 4 ma i ccob-op output buffer current (per channel) 13 ma i ccp-op serdes pll current (per quad) 26 ma i ccax33-op serdes termination current (per quad) 0.01 ma 1. equalization enabled, pre-emphasis disabled. 2. t j = 25?, power supplies at nominal voltage. symbol description typ. 2 units p s-1ch-31 serdes power (one channel @ 3.125 gbps) 90 m w p s-1ch-25 serdes power (one channel @ 2.5 gbps) 87 m w p s-1ch-12 serdes power (one channel @ 1.25 gbps) 86 m w p s-1ch-02 serdes power (one channel @ 250 mbps) 76 m w 1. one quarter of the total quad power (includes contribution from common circuits, all channels in the quad operating, pre-emphasis disabled, equalization enabled). 2. typical values measured at 25 o c and 1.2v.
3-9 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet sysio recommended operating conditions standard v ccio v ref (v) min. typ. max. min. typ. max. lvcmos 3.3 2 3.135 3.3 3.465 lvcmos 2.5 2 2.375 2.5 2.625 lvcmos 1.8 1.71 1.8 1.89 lvcmos 1.5 1.425 1.5 1.575 lvcmos 1.2 2 1.14 1.2 1.26 lvttl 2 3.135 3.3 3.465 pci 3.135 3.3 3.465 sstl18 2 class i, ii 1.71 1.8 1.89 0.833 0.9 0.969 sstl2 2 class i, ii 2.375 2.5 2.625 1.15 1.25 1.35 sstl3 2 class i, ii 3.135 3.3 3.465 1.3 1.5 1.7 hstl 2 15 class i 1.425 1.5 1.575 0.68 0.75 0.9 hstl 2 18 class i, ii 1.71 1.8 1.89 0.816 0.9 1.08 lvds 2 2.375 2.5 2.625 mlvds25 1 2.375 2.5 2.625 lvpecl33 1, 2 3.135 3.3 3.465 blvds25 1, 2 2.375 2.5 2.625 rsds 1, 2 2.375 2.5 2.625 sstl18d_i 2 , ii 2 1.71 1.8 1.89 sstl25d_ i 2 , ii 2 2.375 2.5 2.625 sstl33d_ i 2 , ii 2 3.135 3.3 3.465 hstl15d_ i 2 1.425 1.5 1.575 hstl18d_ i 2 , ii 2 1.71 1.8 1.89 1. inputs on chip. outputs are implemented with the addition of external resistors. 2. input on this standard does not depend on the value of v ccio .
3-10 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet sysio single-ended dc electrical characteristics input/output standard v il v ih v ol max. (v) v oh min. (v) i ol 1 (ma) i oh 1 (ma) min. (v) max. (v) min. (v) max. (v) lvcmos 3.3 -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvttl -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 2.5 -0.3 0.7 1.7 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.8 -0.3 0.35 v ccio 0.65 v ccio 3.6 0.4 v ccio - 0.4 16, 12, 8, 4 -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.5 -0.3 0.35 v ccio 0.65 v ccio 3.6 0.4 v ccio - 0.4 8, 4 -8, -4 0.2 v ccio - 0.2 0.1 -0.1 lvcmos 1.2 -0.3 0.35 v cc 0.65 v cc 3.6 0.4 v ccio - 0.4 6, 2 -6, -2 0.2 v ccio - 0.2 0.1 -0.1 pci -0.3 0.3 v ccio 0.5 v ccio 3.6 0.1 v ccio 0.9 v ccio 1.5 -0.5 sstl3 class i -0.3 v ref - 0.2 v ref + 0.2 3.6 0.7 v ccio - 1.1 8 -8 sstl3 class ii -0.3 v ref - 0.2 v ref + 0.2 3.6 0.5 v ccio - 0.9 16 -16 sstl2 class i -0.3 v ref - 0.18 v ref + 0.18 3.6 0.54 v ccio - 0.62 7.6 -7.6 12 -12 sstl2 class ii -0.3 v ref - 0.18 v ref + 0.18 3.6 0.35 v ccio - 0.43 15.2 -15.2 20 -20 sstl18 class i -0.3 v ref - 0.125 v ref + 0.125 3.6 0.4 v ccio - 0.4 6.7 -6.7 sstl18 class ii -0.3 v ref - 0.125 v ref + 0.125 3.6 0.28 v ccio - 0.28 8-8 11 -11 hstl class i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 4-4 8-8 hstl18 class i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 8-8 12 -12 hstl18 class ii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 16 -16 1. the average dc current drawn by i/os between gnd connections, or between the last gnd in an i/o bank and the end of an i/o ba nk, as shown in the logic signal connections table shall not exceed n * 8ma, where n is the number of i/os between bank gnd connection s or between the last gnd in a bank and the end of a bank.
3-11 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet sysio differential electrical characteristics lvds over recommended operating conditions differential hstl and sstl differential hstl and sstl outputs are implemented as a pair of complementary single-ended outputs. all allow- able single-ended output classes (class i and class ii) are supported in this mode. for further information on lvpecl, rsds, mlvds, blvds and other differential interfaces please see details of additional technical information at the end of this data sheet. parameter description test conditions min. typ. max. units v inp , v inm input voltage 0 2.4 v v cm input common mode voltage half the sum of the two inputs 0.05 2.35 v v thd differential input threshold difference between the two inputs +/-100 mv i in input current power on or power off +/-10 ? v oh output high voltage for v op or v om r t = 100 ohm 1.38 1.60 v v ol output low voltage for v op or v om r t = 100 ohm 0.9v 1.03 v v od output voltage differential (v op - v om ), r t = 100 ohm 250 350 450 mv v od change in v od between high and low 50 mv v os output voltage offset (v op + v om )/2, r t = 100 ohm 1.125 1.20 1.375 v v os change in v os between h and l 50 mv i sa output short circuit current v od = 0v driver outputs shorted to ground 24 ma i sab output short circuit current v od = 0v driver outputs shorted to each other 12 ma
3-12 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet lvds25e the top and bottom sides of latticeecp2/m devices support lvds outputs via emulated complementary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the scheme shown in figure 3-1 is one possible solution for point-to-point signals. figure 3-1. lvds25e output termination example table 3-2. lvds25e dc conditions parameter description typical units v ccio output driver supply (+/-5%) 2.50 v z out driver impedance 20 r s driver series resistor (+/-1%) 158 r p driver parallel resistor (+/-1%) 140 r t receiver termination (+/-1%) 100 v oh output high voltage 1.43 v v ol output low voltage 1.07 v v od output differential voltage 0.35 v v cm output common mode voltage 1.25 v z back back impedance 100.5 i dc dc output current 6.03 ma + - rs=15 8 ohms (? % ) rs=15 8 ohms (? % ) rp = 140 ohms (? % ) rt = 100 ohms (? % ) off-chip transmission line, zo = 100 ohm differential v ccio = 2.5 v (? % ) 8 ma v ccio = 2.5 v (? % ) o n -chip off-chip o n -chip 8 ma
3-13 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet blvds the latticeecp2/m devices support the blvds standard. this standard is emulated using complementary lvc- mos outputs in conjunction with a parallel external resistor across the driver outputs. blvds is intended for use when multi-drop and bi-directional multi-point differential signaling is required. the scheme shown in figure 3-2 is one possible solution for bi-directional multi-point differential signals. figure 3-2. blvds multi-point output example table 3-3. blvds dc conditions 1 over recommended operating conditions parameter description typical units zo = 45 zo = 90 v ccio output driver supply (+/- 5%) 2.50 2.50 v z out driver impedance 10.00 10.00 r s driver series resistor (+/- 1%) 90.00 90.00 r tl driver parallel resistor (+/- 1%) 45.00 90.00 r tr receiver termination (+/- 1%) 45.00 90.00 v oh output high voltage 1.38 1.48 v v ol output low voltage 1.12 1.02 v v od output differential voltage 0.25 0.46 v v cm output common mode voltage 1.25 1.25 v i dc dc output current 11.24 10.20 ma 1. for input buffer, see lvds table. heavily loaded backplane, effective zo ~ 45 to 90 ohms differential 2.5v r tl r tr r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms r s = 90 ohms 45-90 ohms 45-90 ohms 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v + - . . . + - . . . + - + - 16ma 16ma 16ma 16ma 16ma 16ma 16ma 16ma
3-14 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet lvpecl the latticeecp2/m devices support the differential lvpecl standard. this standard is emulated using comple- mentary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the lvpecl input stan- dard is supported by the lvds differential input buffer. the scheme shown in figure 3-3 is one possible solution for point-to-point signals. figure 3-3. differential lvpecl table 3-4. lvpecl dc conditions 1 over recommended operating conditions parameter description typical units v ccio output driver supply (+/-5%) 3.30 v z out driver impedance 10 r s driver series resistor (+/-1%) 93 r p driver parallel resistor (+/-1%) 196 r t receiver termination (+/-1%) 100 v oh output high voltage 2.05 v v ol output low voltage 1.25 v v od output differential voltage 0.80 v v cm output common mode voltage 1.65 v z back back impedance 100.5 i dc dc output current 12.11 ma 1. for input buffer, see lvds table. transmission line, zo = 100 ohm differential off-chip on-chip v ccio = 3.3v (+/-5%) v ccio = 3.3v (+/-5%) r p = 196 ohms (+/-1%) r t = 100 ohms (+/-1%) r s = 93.1 ohms (+/-1%) r s = 93.1 ohms (+/-1%) 16ma 16ma + - off-chip on-chip
3-15 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet rsds the latticeecp2/m devices support differential rsds standard. this standard is emulated using complementary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the rsds input standard is sup- ported by the lvds differential input buffer. the scheme shown in figure 3-4 is one possible solution for rsds standard implementation. resistor values in figure 3-4 are industry standard values for 1% resistors. figure 3-4. rsds (reduced swing differential signaling) table 3-5. rsds dc conditions 1 over recommended operating conditions parameter description typical units v ccio output driver supply (+/-5%) 2.50 v z out driver impedance 20 r s driver series resistor (+/-1%) 294 r p driver parallel resistor (+/-1%) 121 r t receiver termination (+/-1%) 100 v oh output high voltage 1.35 v v ol output low voltage 1.15 v v od output differential voltage 0.20 v v cm output common mode voltage 1.25 v z back back impedance 101.5 i dc dc output current 3.66 ma 1. for input buffer, see lvds table. r s = 294 ohms (+/-1%) r s = 294 ohms (+/-1%) r p = 121 ohms (+/-1%) r t = 100 ohms (+/-1%) on-chip on-chip 8ma 8ma v ccio = 2.5v (+/-5%) v ccio = 2.5v (+/-5%) transmission line, zo = 100 ohm differential + - off-chip off-chip
3-16 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet mlvds the latticeecp2/m devices support the differential mlvds standard. this standard is emulated using complemen- tary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the mlvds input standard is supported by the lvds differential input buffer. the scheme shown in figure 3-5 is one possible solution for mlvds standard implementation. resistor values in figure 3-5 are industry standard values for 1% resistors. figure 3-5. mlvds (multipoint low voltage differential signaling) table 3-6. mlvds dc conditions 1 for further information on lvpecl, rsds, mlvds, blvds and other differential interfaces please see details of additional technical information at the end of this data sheet. parameter description typical units zo=50 zo=70 v ccio output driver supply (+/-5%) 2.50 2.50 v z out driver impedance 10.00 10.00 r s driver series resistor (+/-1%) 35.00 35.00 r tl driver parallel resistor (+/-1%) 50.00 70.00 r tr receiver termination (+/-1%) 50.00 70.00 v oh output high voltage 1.52 1.60 v v ol output low voltage 0.98 0.90 v v od output differential voltage 0.54 0.70 v v cm output common mode voltage 1.25 1.25 v i dc dc output current 21.74 20.00 ma 1. for input buffer, see lvds table. 16ma 2.5v 2.5v + - 2.5v 2.5v + - 2.5v 2.5v + - . . . . . . a m 6 1 heavily loaded backplace, effective zo~50 to 70 ohms differential 50 to 70 ohms +/-1% 50 to 70 ohms +/-1% r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r s = 35ohms r tr r tl 16ma 2.5v a m 6 1 2.5v + - a m 6 1 2.5v a m 6 1 2.5v + - 16ma 16ma
3-17 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet typical building block function performance 1 pin-to-pin performance (lvcmos25 12ma drive) function -7 timing units basic functions 16-bit decoder 3.8 ns 32-bit decoder 4.5 ns 64-bit decoder 5.0 ns 4:1 mux 3.2 ns 8:1 mux 3.4 ns 16:1 mux 3.5 ns 32:1 mux 4.0 ns 1. these timing numbers were generated using the isplever design tool. exact performance may vary with device and tool version. the tool uses internal parameters that have been characterized but are not tested on every device. timing v.a 0.10 register-to-register performance function -7 timing units basic functions 16-bit decoder 599 mhz 32-bit decoder 542 mhz 64-bit decoder 417 mhz 4:1 mux 847 mhz 8:1 mux 803 mhz 16:1 mux 660 mhz 32:1 mux 577 mhz 8-bit adder 591 mhz 16-bit adder 500 mhz 64-bit adder 306 mhz 16-bit counter 488 mhz 32-bit counter 378 mhz 64-bit counter 260 mhz 64-bit accumulator 253 mhz embedded memory functions 512x36 single port ram, ebr output registers 370 mhz 1024x18 true-dual port ram ( w rite through or normal, ebr output regis- ters) 370 mhz 1024x18 true-dual port ram (read- before- w rite, ebr output registers) 294 mhz 1024x18 true-dual port ram ( w rite through or normal, plc output registers) 280 mhz distributed memory functions 16x4 pseudo-dual port ram (one pfu) 819 mhz 32x4 pseudo-dual port ram 521 mhz 64x8 pseudo-dual port ram 435 mhz
3-18 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet derating timing tables logic timing provided in the following sections of this data sheet and the isplever design tools are worst case numbers in the operating range. actual delays at nominal temperature and voltage for best case process, can be much better than the values given in the tables. the isplever design tool can provide logic timing numbers at a particular temperature and voltage. dsp functions 18x18 multiplier (all registers) 420 mhz 9x9 multiplier (all registers) 420 mhz 36x36 multiplier (all registers) 372 mhz 18x18 multiplier/accumulate (input and output registers) 323 mhz 18x18 multiplier-add/sub-sum (all reg- isters) 420 mhz dsp ip functions 16-tap fully-parallel fir filter 304 mhz 1024-pt, radix 4, decimation in frequency fft 227 mhz 8x8 matrix multiplier 223 mhz timing v.a 0.10 register-to-register performance (continued) function -7 timing units
3-19 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet latticeecp2/m external switching characteristics 9 over recommended operating conditions parameter description device -7 -6 -5 units min. max. min. max. min. max. general i/o pin parameters (using primary clock without pll) 1 t co clock to output - pio output register lfe2-6 3.50 3.90 4.20 ns lfe2-12 3.50 3.90 4.20 ns lfe2-20 3.50 3.90 4.20 ns lfe2-35 3.50 3.90 4.20 ns lfe2-50 3.50 3.90 4.20 ns lfe2-70 3.70 4.10 4.40 ns lfe2m20 3.90 4.30 4.70 ns lfe2m35 3.90 4.30 4.70 ns t su clock to data setup - pio input register lfe2-6 0.00 0.00 0.00 ns lfe2-12 0.00 0.00 0.00 ns lfe2-20 0.00 0.00 0.00 ns lfe2-35 0.00 0.00 0.00 ns lfe2-50 0.00 0.00 0.00 ns lfe2-70 0.00 0.00 0.00 ns lfe2m20 0.00 0.00 0.00 ns lfe2m35 0.00 0.00 0.00 ns t h clock to data hold - pio input register lfe2-6 1.40 1.70 1.90 ns lfe2-12 1.40 1.70 1.90 ns lfe2-20 1.40 1.70 1.90 ns lfe2-35 1.40 1.70 1.90 ns lfe2-50 1.40 1.70 1.90 ns lfe2-70 1.40 1.70 1.90 ns lfe2m20 1.40 1.70 1.90 ns lfe2m35 1.40 1.70 1.90 ns t su_del clock to data setup - pio input register with data input delay lfe2-6 1.40 1.70 1.90 ns lfe2-12 1.40 1.70 1.90 ns lfe2-20 1.40 1.70 1.90 ns lfe2-35 1.40 1.70 1.90 ns lfe2-50 1.40 1.70 1.90 ns lfe2-70 1.40 1.70 1.90 ns lfe2m20 1.40 1.70 1.90 ns lfe2m35 1.40 1.70 1.90 ns t h_del clock to data hold - pio input reg- ister with input data delay lfe2-6 0.00 0.00 0.00 ns lfe2-12 0.00 0.00 0.00 ns lfe2-20 0.00 0.00 0.00 ns lfe2-35 0.00 0.00 0.00 ns lfe2-50 0.00 0.00 0.00 ns lfe2-70 0.00 0.00 0.00 ns lfe2m20 0.00 0.00 0.00 ns lfe2m35 0.00 0.00 0.00 ns
3-20 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet f max_io clock frequency of i/o register and pfu register ecp2/m 420 357 311 mhz general i/o pin parameters (using edge clock without pll) 1 t coe clock to output - pio output register lfe2-6 2.60 2.90 3.20 ns lfe2-12 2.60 2.90 3.20 ns lfe2-20 2.60 2.90 3.20 ns lfe2-35 2.60 2.90 3.20 ns lfe2-50 2.60 2.90 3.20 ns lfe2-70 2.60 2.90 3.20 ns lfe2m20 2.60 2.90 3.20 ns lfe2m35 2.60 2.90 3.20 ns t sue clock to data setup - pio input register lfe2-6 0.00 0.00 0.00 ns lfe2-12 0.00 0.00 0.00 ns lfe2-20 0.00 0.00 0.00 ns lfe2-35 0.00 0.00 0.00 ns lfe2-50 0.00 0.00 0.00 ns lfe2-70 0.00 0.00 0.00 ns lfe2m20 0.00 0.00 0.00 ns lfe2m35 0.00 0.00 0.00 ns t he clock to data hold - pio input register lfe2-6 0.90 1.10 1.30 ns lfe2-12 0.90 1.10 1.30 ns lfe2-20 0.90 1.10 1.30 ns lfe2-35 0.90 1.10 1.30 ns lfe2-50 0.90 1.10 1.30 ns lfe2-70 0.90 1.10 1.30 ns lfe2m20 0.90 1.10 1.30 ns lfe2m35 0.90 1.10 1.30 ns t su_dele clock to data setup - pio input register with data input delay lfe2-6 1.00 1.30 1.60 ns lfe2-12 1.00 1.30 1.60 ns lfe2-20 1.00 1.30 1.60 ns lfe2-35 1.00 1.30 1.60 ns lfe2-50 1.00 1.30 1.60 ns lfe2-70 1.00 1.30 1.60 ns lfe2m20 1.20 1.60 1.90 ns lfe2m35 1.20 1.60 1.90 ns latticeecp2/m external switching characteristics 9 (continued) over recommended operating conditions parameter description device -7 -6 -5 units min. max. min. max. min. max.
3-21 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet t h_del clock to data hold - pio input register with input data delay lfe2-6 0.00 0.00 0.00 ns lfe2-12 0.00 0.00 0.00 ns lfe2-20 0.00 0.00 0.00 ns lfe2-35 0.00 0.00 0.00 ns lfe2-50 0.00 0.00 0.00 ns lfe2-70 0.00 0.00 0.00 ns lfe2m20 0.00 0.00 0.00 ns lfe2m35 0.00 0.00 0.00 ns f max_ioe clock frequency of i/o and pfu register ecp2/m 420 357 311 mhz general i/o pin parameters (using primary clock with pll) 1 t copll 10 clock to output - pio output register lfe2-6 2.30 2.60 2.80 ns lfe2-12 2.30 2.60 2.80 ns lfe2-20 2.30 2.60 2.80 ns lfe2-35 2.30 2.60 2.80 ns lfe2-50 2.30 2.60 2.80 ns lfe2-70 2.30 2.60 2.80 ns lfe2m20 2.30 2.60 2.80 ns lfe2m35 2.30 2.60 2.80 ns t supll clock to data setup - pio input register lfe2-6 0.70 0.80 0.90 ns lfe2-12 0.70 0.80 0.90 ns lfe2-20 0.70 0.80 0.90 ns lfe2-35 0.70 0.80 0.90 ns lfe2-50 0.70 0.80 0.90 ns lfe2-70 0.70 0.80 0.90 ns lfe2m20 0.70 0.80 0.90 ns lfe2m35 0.70 0.80 0.90 ns t hpll clock to data hold - pio input register lfe2-6 1.00 1.20 1.40 ns lfe2-12 1.00 1.20 1.40 ns lfe2-20 1.00 1.20 1.40 ns lfe2-35 1.00 1.20 1.40 ns lfe2-50 1.00 1.20 1.40 ns lfe2-70 1.00 1.20 1.40 ns lfe2m20 1.00 1.20 1.40 ns lfe2m35 1.00 1.20 1.40 ns latticeecp2/m external switching characteristics 9 (continued) over recommended operating conditions parameter description device -7 -6 -5 units min. max. min. max. min. max.
3-22 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet t su_delpll clock to data setup - pio input register with data input delay lfe2-6 1.80 2.00 2.20 ns lfe2-12 1.80 2.00 2.20 ns lfe2-20 1.80 2.00 2.20 ns lfe2-35 1.80 2.00 2.20 ns lfe2-50 1.80 2.00 2.20 ns lfe2-70 1.80 2.00 2.20 ns lfe2m20 1.80 2.00 2.20 ns lfe2m35 1.80 2.00 2.20 ns t h_delpll clock to data hold - pio input register with input data delay lfe2-6 0.00 0.00 0.00 ns lfe2-12 0.00 0.00 0.00 ns lfe2-20 0.00 0.00 0.00 ns lfe2-35 0.00 0.00 0.00 ns lfe2-50 0.00 0.00 0.00 ns lfe2-70 0.00 0.00 0.00 ns lfe2m20 0.00 0.00 0.00 ns lfe2m35 0.00 0.00 0.00 ns ddr i/o pin parameters 2 t dvadq data valid after dqs (ddr read) ecp2/m 0.225 0.225 0.225 ui t dvedq data hold after dqs (ddr read) ecp2/m 0.640 0.640 0.640 ui t dqvbs data valid before dqs (ddr w rite) ecp2/m 0.250 0.250 0.250 ui t dqvas data valid after dqs (ddr w rite) ecp2/m 0.250 0.250 0.250 ui f max_ddr ddr clock frequency 6 ecp2/m 95 200 95 166 95 133 mhz ddr2 i/o pin parameters 3 t dvadq data valid after dqs (ddr read) ecp2/m 0.225 0.225 0.225 ui t dvedq data hold after dqs (ddr read) ecp2/m 0.640 0.640 0.640 ui t dqvbs data valid before dqs (ddr w rite) ecp2/m 0.250 0.250 0.250 ui t dqvas data valid after dqs (ddr w rite) ecp2/m 0.250 0.250 0.250 ui f max_ddr2 ddr clock frequency ecp2/m 133 266 133 200 133 166 mhz spi4.2 i/o pin parameters static alignment 4, 8, 11 maximum data rate ecp2-20 750 622 622 mbps ecp2-35 750 622 622 mbps ecp2-50 750 622 622 mbps ecp2-70 750 622 622 mbps ecp2m20 650 622 622 mbps ecp2m35 650 622 622 mbps t dvaclkspi data valid after clk (receive) ecp2-20 0.26 0.26 0.26 ui ecp2-35 0.26 0.26 0.26 ui ecp2-50 0.26 0.26 0.26 ui ecp2-70 0.26 0.26 0.26 ui ecp2m20 0.26 0.26 0.26 ui ecp2m35 0.26 0.26 0.26 ui latticeecp2/m external switching characteristics 9 (continued) over recommended operating conditions parameter description device -7 -6 -5 units min. max. min. max. min. max.
3-23 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet t dveclkspi data hold after clk (receive) ecp2-20 0.74 0.74 0.74 ui ecp2-35 0.74 0.74 0.74 ui ecp2-50 0.74 0.74 0.74 ui ecp2-70 0.74 0.74 0.74 ui ecp2m20 0.78 0.78 0.78 ui ecp2m35 0.78 0.78 0.78 ui t diaspi data invalid after clock (transmit) ecp2-20 280 280 280 ps ecp2-35 280 280 280 ps ecp2-50 280 280 280 ps ecp2-70 280 280 280 ps ecp2m20 280 280 280 ps ecp2m35 280 280 280 ps t dibspi data invalid before clock (transmit) ecp2-20 280 280 280 ps ecp2-35 280 280 280 ps ecp2-50 280 280 280 ps ecp2-70 280 280 280 ps ecp2m20 280 280 280 ps ecp2m35 280 280 280 ps xgmii i/o pin parameters (312 mbps) 5 t suxgmii data setup before read clock ecp2/m 480 480 480 ps t hxgmii data hold after read clock ecp2/m 480 480 480 ps t dvbckxgmii data valid before clock ecp2/m 960 960 960 ps t dvackxgmii data valid after clock ecp2/m 960 960 960 ps primary f max_pri 7 frequency for primary clock tree ecp2/m 420 357 311 mhz t w _pri clock pulse w idth for primary clock ecp2/m 0.95 1.19 2.00 ns t ske w _pri primary clock skew w ithin a bank ecp2/m 300 360 420 ps edge clock f max_edge 7 frequency for edge clock ecp2/m 420 357 311 mhz t w _edge clock pulse w idth for edge clock ecp2/m 0.95 1.19 2.00 ns t ske w _edge edge clock skew w ithin an edge of the device ecp2/m 300 360 420 ps 1. general timing numbers based on lvcmos 2.5, 12ma, 0pf load. 2. ddr timing numbers based on sstl25 for bga packages only. 3. ddr2 timing numbers based on sstl18 for bga packages only. 4. spi4.2 and sfi4 timing numbers based on lvds25 for bga packages only. 5. xgmii timing numbers based on hstl class i. a corresponding left/right dedicated clock buffer is used when using the spi4.2 i nterface to the left or right edge of the device. for spi4.2 mode, the software tool will help in selecting the appropriate clock buffer. 6. ip will be used to support ddr and ddr2 memory data rates down to 95mhz. this approach uses a free-running clock and pfu regi ster to sample the data instead of the hardwired ddr memory interface. 7. using the lvds i/o standard. 8. ecp2-6 and ecp2-12 do not support spi4.2 9. the ac numbers do not apply to pclk6 and pclk7. 10. applies to clkop only. 11. please refer to technical note tn1159, latticeecp2m pin assignment recommendations for best performance. timing v.a 0.10 latticeecp2/m external switching characteristics 9 (continued) over recommended operating conditions parameter description device -7 -6 -5 units min. max. min. max. min. max.
3-24 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet figure 3-6. spi4.2 parameters transmit parameters receiver parameters t dvaclkspi t dveclkspi t diaspi t dibspi t diaspi t dibspi data (rdat,rctl) rdtclk t dveclkspi t dvaclkspi clk data (tdat, tctl)
3-25 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet figure 3-7. ddr and ddr2 parameters figure 3-8. xgmii parameters transmit parameters receiver parameters t dqvbs t dqvas t dqvbs t dqvas dqs dq dqs dq t dvadq t dvedq t dvedq t dvadq transmit parameters receiver parameters t t t t clock data clock data t suxgmii t hxgmii t suxgmii t hxgmii d v bckxgmii d v ackxgmii d v ackxgmii d v bckxgmii
3-26 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet latticeecp2/m internal switching characteristics 1 over recommended operating conditions parameter description -7 -6 -5 units min. max. min. max. min. max. pfu/pff logic mode timing t lut4_pfu lut4 delay (a to d inputs to f output) 0.180 0.198 0.216 ns t lut6_pfu lut6 delay (a to d inputs to ofx output) 0.304 0.331 0.358 ns t lsr_pfu set/reset to output of pfu (asynchro- nous) 0.600 0.655 0.711 ns t sum_pfu clock to mux (m0,m1) input setup time 0.128 0.129 0.129 ns t hm_pfu clock to mux (m0,m1) input hold time -0.051 -0.049 -0.046 ns t sud_pfu clock to d input setup time 0.061 0.071 0.081 ns t hd_pfu clock to d input hold time 0.002 0.003 0.003 ns t ck2q_pfu clock to q delay, (d-type register con?u- ration) 0.285 0.309 0.333 ns pfu dual port memory mode timing t coram_pfu clock to output (f port) 0.902 1.083 1.263 ns t sudata_pfu data setup time -0.172 -0.205 -0.238 ns t hdata_pfu data hold time 0.199 0.235 0.271 ns t suaddr_pfu address setup time -0.245 -0.284 -0.323 ns t haddr_pfu address hold time 0.246 0.285 0.324 ns t su w ren_pfu w rite/read enable setup time -0.122 -0.145 -0.168 ns t h w ren_pfu w rite/read enable hold time 0.132 0.156 0.180 ns pic timing pio input/output buffer timing t in_pio input buffer delay (lvcmos25) 0.613 0.681 0.749 ns t out_pio output buffer delay (lvcmos25) 1.115 1.115 1.343 ns iologic input/output timing t sui_pio input register setup time (data before clock) 0.596 0.645 0.694 ns t hi_pio input register hold time (data after clock) -0.570 -0.614 -0.658 ns t coo_pio output register clock to output delay 0.61 0.66 0.72 ns t suce_pio input register clock enable setup time 0.032 0.037 0.041 ns t hce_pio input register clock enable hold time -0.022 -0.025 -0.028 ns t sulsr_pio set/reset setup time 0.184 0.201 0.217 ns t hlsr_pio set/reset hold time -0.080 -0.086 -0.093 ns ebr timing t co_ebr clock (read) to output from address or data 2.51 2.75 2.99 ns t coo_ebr clock ( w rite) to output from ebr output register 0.33 0.36 0.39 ns t sudata_ebr setup data to ebr memory -0.157 -0.181 -0.205 ns t hdata_ebr hold data to ebr memory 0.173 0.195 0.217 ns t suaddr_ebr setup address to ebr memory -0.115 -0.130 -0.145 ns t haddr_ebr hold address to ebr memory 0.138 0.155 0.172 ns t su w ren_ebr setup w rite/read enable to pfu memory -0.128 -0.149 -0.170 ns
3-27 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet t h w ren_ebr hold w rite/read enable to pfu memory 0.139 0.156 0.173 ns t suce_ebr clock enable setup time to ebr output register 0.123 0.134 0.145 ns t hce_ebr clock enable hold time to ebr output register -0.081 -0.090 -0.100 ns t rsto_ebr reset to output delay time from ebr output register 1.03 1.15 1.26 ns t sube_ebr byte enable set-up time to ebr output register -0.115 -0.130 -0.145 ns t hbe_ebr byte enable hold time to ebr output register 0.138 0.155 0.172 ns gpll parameters t rstrec_gpll reset recovery to rising clock 1.00 1.00 1.00 ns spll parameters t rstrec_spll reset recovery to rising clock 1.00 1.00 1.00 ns dsp block timing 2,3 t sui_dsp input register setup time 0.12 0.13 0.14 ns t hi_dsp input register hold time 0.02 -0.01 -0.03 ns t sup_dsp pipeline register setup time 2.18 2.42 2.66 ns t thp_dsp pipeline register hold time -0.68 -0.77 -0.86 ns t suo_dsp output register setup time 4.26 4.71 5.16 ns t ho_dsp output register hold time -1.25 -1.40 -1.54 ns t coi_dsp input register clock to output time 3.92 4.30 4.68 ns t cop_dsp pipeline register clock to output time 1.87 1.98 2.08 ns t coo_dsp output register clock to output time 0.50 0.52 0.55 ns t suaddsub addsub input register setup time -0.24 -0.26 -0.28 ns t haddsub addsub input register hold time 0.27 0.29 0.32 ns 1. internal parameters are characterized but not tested on every device. 2. these parameters apply to latticeecp devices only. 3. dsp block is con?ured in multiply add/sub 18x18 mode. timing v.a 0.10 latticeecp2/m internal switching characteristics 1 (continued) over recommended operating conditions parameter description -7 -6 -5 units min. max. min. max. min. max.
3-28 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet timing diagrams figure 3-9. read/write mode (normal) note: input data and address are registered at the positive edge of the clock and output data appears after the positive edge o f the clock. figure 3-10. read/write mode with input and output registers a0 a1 a0 a1 d0 d1 doa a0 t access t access t su t h d0 d1 d0 dia ada wea csa clka a0 a1 a0 a0 d0 d1 d0 d0 doa output is only updated during a read cycle a1 d1 d0 d1 mem(n) data from previous read mem(n) data from previous read dia ada wea csa clka doa doa (regs) t su t h t access t access
3-29 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet figure 3-11. read before write (sp read/write on port a, input registers only) note: input data and address are registered at the positive edge of the clock and output data appears after the positive edge o f the clock. figure 3-12. write through (sp read/write on port a, input registers only) note: input data and address are registered at the positive edge of the clock and output data appears after the positive edge o f the clock. a0 a1 a0 a1 d0 d1 d2 doa a0 d2 d3 d1 old a0 data old a1 data d0 d1 dia ada wea csa clka t su t h t access t access t access t access t access a0 a1 a0 d0 d1 d4 t su t access t access t access t h d2 d3 d4 d0 d1 d2 data from prev read or write three consecutive writes to a0 d3 doa dia ada wea csa clka t access
3-30 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet latticeecp2/m family timing adders 1, 2, 3 over recommended operating conditions buffer type description -7 -6 -5 units input adjusters lvds25e lvdse -0.04 -0.07 -0.10 ns lvds25 lvds -0.04 -0.02 0.00 ns blvds25 blvds -0.04 -0.09 -0.15 ns mlvds lvds -0.15 -0.15 -0.15 ns rsds rsds -0.15 -0.15 -0.15 ns lvpecl33 lvpecl 0.16 0.15 0.13 ns hstl18_i hstl_18 class i 0.01 -0.01 -0.04 ns hstl18_ii hstl_18 class ii 0.01 -0.01 -0.04 ns hstl18d_i differential hstl 18 class i 0.01 -0.01 -0.04 ns hstl18d_ii differential hstl 18 class ii 0.01 -0.01 -0.04 ns hstl15_i hstl_15 class i 0.01 -0.01 -0.04 ns hstl15d_i differential hstl 15 class i 0.01 -0.01 -0.04 ns sstl33_i sstl_3 class i -0.03 -0.07 -0.10 ns sstl33_ii sstl_3 class ii -0.03 -0.07 -0.10 ns sstl33d_i differential sstl_3 class i -0.03 -0.07 -0.10 ns sstl33d_ii differential sstl_3 class ii -0.03 -0.07 -0.10 ns sstl25_i sstl_2 class i -0.04 -0.07 -0.10 ns sstl25_ii sstl_2 class ii -0.04 -0.07 -0.10 ns sstl25d_i differential sstl_2 class i -0.04 -0.07 -0.10 ns sstl25d_ii differential sstl_2 class ii -0.04 -0.07 -0.10 ns sstl18_i sstl_18 class i -0.01 -0.04 -0.07 ns sstl18_ii sstl_18 class ii -0.01 -0.04 -0.07 ns sstl18d_i differential sstl_18 class i -0.01 -0.04 -0.07 ns sstl18d_ii differential sstl_18 class ii -0.01 -0.04 -0.07 ns lvttl33 lvttl -0.16 -0.16 -0.16 ns lvcmos33 lvcmos 3.3 -0.08 -0.12 -0.16 ns lvcmos25 lvcmos 2.5 0.00 0.00 0.00 ns lvcmos18 lvcmos 1.8 -0.16 -0.17 -0.17 ns lvcmos15 lvcmos 1.5 -0.14 -0.14 -0.14 ns lvcmos12 lvcmos 1.2 -0.04 -0.01 0.01 ns pci33 pci -0.08 -0.12 -0.16 ns output adjusters lvds25e lvds 2.5 e 4 0.25 0.19 0.13 ns lvds25 lvds 2.5 0.10 0.13 0.17 ns blvds25 blvds 2.5 0.00 -0.01 -0.03 ns mlvds mlvds 2.5 4 0.00 -0.01 -0.03 ns rsds rsds 2.5 4 0.25 0.19 0.13 ns lvpecl33 lvpecl 3.3 4 -0.02 -0.04 -0.06 ns hstl18_i hstl_18 class i 8ma drive -0.19 -0.22 -0.25 ns hstl18_ii hstl_18 class ii -0.30 -0.34 -0.37 ns hstl18d_i differential hstl 18 class i 8ma drive -0.19 -0.22 -0.25 ns
3-31 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet hstl18d_ii differential hstl 18 class ii -0.30 -0.34 -0.37 ns hstl15_i hstl_15 class i 4ma drive -0.22 -0.25 -0.27 ns hstl15d_i differential hstl 15 class i 4ma drive -0.22 -0.25 -0.27 ns sstl33_i sstl_3 class i -0.12 -0.15 -0.18 ns sstl33_ii sstl_3 class ii -0.20 -0.23 -0.27 ns sstl33d_i differential sstl_3 class i -0.12 -0.15 -0.18 ns sstl33d_ii differential sstl_3 class ii -0.20 -0.23 -0.27 ns sstl25_i sstl_2 class i 8ma drive -0.16 -0.19 -0.22 ns sstl25_ii sstl_2 class ii 16ma drive -0.19 -0.22 -0.25 ns sstl25d_i differential sstl_2 class i 8ma drive -0.16 -0.19 -0.22 ns sstl25d_ii differential sstl_2 class ii 16ma drive -0.19 -0.22 -0.25 ns sstl18_i sstl_1.8 class i -0.14 -0.17 -0.20 ns sstl18_ii sstl_1.8 class ii 8ma drive -0.20 -0.23 -0.25 ns sstl18d_i differential sstl_1.8 class i -0.14 -0.17 -0.20 ns sstl18d_ii differential sstl_1.8 class ii 8ma drive -0.20 -0.23 -0.25 ns lvttl33_4ma lvttl 4ma drive 0.52 0.60 0.68 ns lvttl33_8ma lvttl 8ma drive 0.06 0.08 0.09 ns lvttl33_12ma lvttl 12ma drive 0.04 0.04 0.05 ns lvttl33_16ma lvttl 16ma drive 0.03 0.02 0.02 ns lvttl33_20ma lvttl 20ma drive -0.09 -0.09 -0.10 ns lvcmos33_4ma lvcmos 3.3 4ma drive, fast slew rate 0.52 0.60 0.68 ns lvcmos33_8ma lvcmos 3.3 8ma drive, fast slew rate 0.06 0.08 0.09 ns lvcmos33_12ma lvcmos 3.3 12ma drive, fast slew rate 0.04 0.04 0.05 ns lvcmos33_16ma lvcmos 3.3 16ma drive, fast slew rate 0.03 0.02 0.02 ns lvcmos33_20ma lvcmos 3.3 20ma drive, fast slew rate -0.09 -0.09 -0.10 ns lvcmos25_4ma lvcmos 2.5 4ma drive, fast slew rate 0.41 0.47 0.53 ns lvcmos25_8ma lvcmos 2.5 8ma drive, fast slew rate 0.01 0.01 0.00 ns lvcmos25_12ma lvcmos 2.5 12ma drive, fast slew rate 0.00 0.00 0.00 ns lvcmos25_16ma lvcmos 2.5 16ma drive, fast slew rate 0.04 0.04 0.04 ns lvcmos25_20ma lvcmos 2.5 20ma drive, fast slew rate -0.09 -0.10 -0.11 ns lvcmos18_4ma lvcmos 1.8 4ma drive, fast slew rate 0.37 0.40 0.43 ns lvcmos18_8ma lvcmos 1.8 8ma drive, fast slew rate 0.10 0.12 0.13 ns lvcmos18_12ma lvcmos 1.8 12ma drive, fast slew rate -0.02 -0.02 -0.02 ns lvcmos18_16ma lvcmos 1.8 16ma drive, fast slew rate -0.02 -0.03 -0.03 ns lvcmos15_4ma lvcmos 1.5 4ma drive, fast slew rate 0.29 0.31 0.32 ns lvcmos15_8ma lvcmos 1.5 8ma drive, fast slew rate 0.05 0.05 0.06 ns lvcmos12_2ma lvcmos 1.2 2ma drive, fast slew rate 0.58 0.69 0.79 ns lvcmos12_6ma lvcmos 1.2 6ma drive, fast slew rate 0.13 0.19 0.26 ns lvcmos33_4ma lvcmos 3.3 4ma drive, slow slew rate 2.17 2.44 2.71 ns lvcmos33_8ma lvcmos 3.3 8ma drive, slow slew rate 2.50 2.67 2.83 ns lvcmos33_12ma lvcmos 3.3 12ma drive, slow slew rate 1.72 1.88 2.05 ns lvcmos33_16ma lvcmos 3.3 16ma drive, slow slew rate 1.64 1.63 1.62 ns latticeecp2/m family timing adders 1, 2, 3 (continued) over recommended operating conditions buffer type description -7 -6 -5 units
3-32 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet lvcmos33_20ma lvcmos 3.3 20ma drive, slow slew rate 1.33 1.36 1.39 ns lvcmos25_4ma lvcmos 2.5 4ma drive, slow slew rate 2.18 2.26 2.33 ns lvcmos25_8ma lvcmos 2.5 8ma drive, slow slew rate 2.19 2.35 2.51 ns lvcmos25_12ma lvcmos 2.5 12ma drive, slow slew rate 1.50 1.66 1.82 ns lvcmos25_16ma lvcmos 2.5 16ma drive, slow slew rate 1.60 1.59 1.58 ns lvcmos25_20ma lvcmos 2.5 20ma drive, slow slew rate 1.43 1.39 1.34 ns lvcmos18_4ma lvcmos 1.8 4ma drive, slow slew rate 2.22 2.27 2.32 ns lvcmos18_8ma lvcmos 1.8 8ma drive, slow slew rate 1.93 2.08 2.23 ns lvcmos18_12ma lvcmos 1.8 12ma drive, slow slew rate 1.43 1.51 1.58 ns lvcmos18_16ma lvcmos 1.8 16ma drive, slow slew rate 1.47 1.46 1.45 ns lvcmos15_4ma lvcmos 1.5 4ma drive, slow slew rate 2.32 2.38 2.43 ns lvcmos15_8ma lvcmos 1.5 8ma drive, slow slew rate 1.84 1.98 2.12 ns lvcmos12_2ma lvcmos 1.2 2ma drive, slow slew rate 2.52 2.63 2.74 ns lvcmos12_6ma lvcmos 1.2 6ma drive, slow slew rate 1.69 1.83 1.96 ns pci33 pci33 0.04 0.04 0.04 ns 1. timing adders are characterized but not tested on every device. 2. lvcmos timing measured with the load speci?d in switching test condition table. 3. all other standards tested according to the appropriate speci?ations. 4. these timing adders are measured with the recommended resistor values. timing v.a 0.10 latticeecp2/m family timing adders 1, 2, 3 (continued) over recommended operating conditions buffer type description -7 -6 -5 units
3-33 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet sysclock gpll timing over recommended operating conditions parameter description conditions min. typ. max. units f in input clock frequency (clki, clkfb) w ithout external capacitor 20 420 mhz w ith external capacitor 5, 6 2 420 mhz f out output clock frequency (clkop, clkos) w ithout external capacitor 25 420 mhz w ith external capacitor 5 5 50 mhz f out2 k-divider output frequency (clkok) w ithout external capacitor 0.195 210 mhz w ith external capacitor 5 0.039 25 mhz f vco pll vco frequency 640 1280 mhz f pfd phase detector input frequency w ithout external capacitor 25 420 mhz w ith external capacitor 5, 6 2 50 mhz ac characteristics t dt output clock duty cycle default duty cycle selected 3 45 50 55 % t ph 4 output phase accuracy ?.05 ui t opjit 1 output clock period jitter f out 100 mhz ?25 ps 50 f out < 100 mhz 0.025 uipp f out < 50 mhz 0.04 uipp t sk input clock to output clock skew n/m = integer ?50 ps t w output clock pulse w idth at 90% or 10% 1 ns t lock 2 pll lock-in time w ithout external capacitor 150 ? w ith external capacitor 5 500 ? t pa programmable delay unit 85 130 360 ps t ipjit input clock period jitter ?00 ps t fbkdly external feedback delay 10 ns t hi input clock high time 90% to 90% 0.5 ns t lo input clock low time 10% to 10% 0.5 ns t rst rst pulse w idth (resetm/resetk) 15 ns reset signal pulse w idth (cntrst) w ithout external capacitor 500 ns w ith external capacitor 5 20 ? 1. jitter sample is taken over 10,000 samples of the primary pll output with clean reference clock and no additional i/o pins to ggling. 2. output clock is valid after t lock for pll reset and dynamic delay adjustment. 3. using lvds output buffers. 4. relative to clkop. 5. value of external capacitor: 5.6 nf ?0%, npo dielectric, ceramic chip capacitor, 1206 or smaller package, connected to pllca p pin. 6. f out (max) = f in * 10 for f in < 5mhz. timing v.a 0.10
3-34 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet sysclock spll timing over recommended operating conditions parameter description conditions min. typ. max. units f in input clock frequency (clki, clkfb) w ithout external capacitor 33 420 mhz w ith external capacitor 5, 6 2 420 mhz f out output clock frequency (clkop, clkos) w ithout external capacitor 33 420 mhz w ith external capacitor 5 5 50 mhz f out2 k-divider output frequency (clkok) w ithout external capacitor 0.258 210 mhz w ith external capacitor 5 0.039 25 mhz f vco pll vco frequency 640 1280 mhz f pfd phase detector input frequency w ithout external capacitor 33 420 mhz w ith external capacitor 6 2 50 mhz ac characteristics t dt output clock duty cycle default duty cycle selected 3 45 50 55 % t ph 4 output phase accuracy ?.05 ui t opjit 1 output clock period jitter f out 100 mhz ?25 ps 50 f out < 100 mhz 0.025 uipp f out < 50 mhz 0.04 uipp t sk input clock to output clock skew divider ratio = integer ?50 ps t w output clock pulse w idth at 90% or 10% 1 ns t lock 2 pll lock-in time w ithout external capacitor 150 ? w ith external capacitor 5 500 ? t ipjit input clock period jitter ?00 ps t fbkdly external feedback delay 10 ns t hi input clock high time 90% to 90% 0.5 ns t lo input clock low time 10% to 10% 0.5 ns t rst rst pulse w idth (resetm/resetk) 15 ns reset signal pulse w idth (cntrst) w ithout external capacitor 500 ns w ith external capacitor 5 20 ? 1. jitter sample is taken over 10,000 samples of the primary pll output with clean reference clock and no additional i/o pins to ggling. 2. output clock is valid after t lock for pll reset and dynamic delay adjustment. 3. using lvds output buffers. 4. phase accuracy of clkos compared to clkop. 5. value of external capacitor: 5.6 nf ?0%, npo dielectric, ceramic chip capacitor, 1206 or smaller package, connected to pllca p pin. 6. f out (max) = f in * 10 for f in < 5mhz. timing v.a 0.10
3-35 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet dll timing over recommended operating conditions parameter description min. typ. max. units f ref input reference clock frequency (on-chip or off-chip) 100 500 mhz f fb feedback clock frequency (on-chip or off-chip) 100 500 mhz f clkop 1 output clock frequency, clkop 100 500 mhz f clkos 2 output clock frequency, clkos 25 500 mhz t pjit output clock period jitter (clean input) 250 ps p-p t cyjit output clock cycle to cycle jitter (clean input) 250 ps p-p t duty output clock duty cycle (at 50% levels, 50% duty cycle input clock, 50% duty cycle circuit turned off, time reference delay mode) 35 65 % t dutytrd output clock duty cycle (at 50% levels, arbitrary duty cycle input clock, 50% duty cycle circuit enabled, time reference delay mode) 40 60 % t dutycir output clock duty cycle (at 50% levels, arbitrary duty cycle input clock, 50% duty cycle circuit enabled, clock injection removal mode) 40 60 % t ske w 3 output clock to clock skew between two outputs with the same phase setting 100 ps t p w h input clock minimum pulse width high (at 80% level) 750 ps t p w l input clock minimum pulse width low (at 20% level) 750 ps t r , t f input clock rise and fall time (20% to 80% levels) 1 ns t instb input clock period jitter +/-250 ps t lock dll lock time 18,500 cycles t rs w d digital reset minimum pulse width (at 80% level) 3 ns t pa delay step size 16.5 42 59.4 ps t range1 max. delay setting for single delay block (144 taps) 2.376 6 8.553 ns t range4 max. delay setting for four chained delay blocks 9.504 24 34.214 ns 1. clkop runs at the same frequency as the input clock. 2. clkos minimum frequency is obtained with divide by 4. 3. this is intended to be a ?ath-matching design guideline and is not a measurable speci?ation. timing v.a 0.10
3-36 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet serdes high speed data transmitter 1 (latticeecp2m family only) table 3-7. serial output timing and levels table 3-8. channel output jitter symbol description fre q uency min. typ. max. units v tx-diff-p-p-1.25 differential swing (1.25v setting) 1, 2 0.25 to 3.125 gbps 1.25 v, p-p v tx-diff-p-p-1.4 differential swing (1.4v setting) 1, 2 0.25 to 3.125 gbps 1.4 v, p-p v tx-diff-p-p-1.0 differential swing (1.0v setting) 1, 2 0.25 to 3.125 gbps 1.0 v, p-p v tx-diff-p-p-1.2 differential swing (1.2v setting) 1, 2 0.25 to 3.125 gbps 1.2 v, p-p v ocm output common mode voltage 0.8 v t tx-r rise time (20% to 80%) 70 ps t tx-f fall time (80% to 20%) 70 ps z tx-oi-se output impedance 50/75/hiz k ohms (single ended) 50/75/ hiz ohms r ltx-rl return loss (with package) 9 db 1. all measurements are with 50 ohm impedance. 2. see technical note tn1124, latticeecp2/m serdes/pcs usage guide for actual binary settings and the min-max range. description fre q uency min. typ. max. units deterministic 3.125 gbps 0.08 0.08 ui, p-p random 3.125 gbps 0.22 0.33 ui, p-p total 3.125 gbps 0.33 0.41 ui, p-p deterministic 2.5gbps 0.05 0.09 ui, p-p random 2.5gbps 0.17 0.30 ui, p-p total 2.5gbps 0.24 0.34 ui, p-p deterministic 1.25 gbps 0.03 0.03 ui, p-p random 1.25 gbps 0.10 0.17 ui, p-p total 1.25 gbps 0.15 0.18 ui, p-p deterministic 250 mbps 0.04 0.04 ui, p-p random 250 mbps 0.12 0.17 ui, p-p total 250 mbps 0.15 0.18 ui, p-p note: values are measured with prbs 2 7 -1, all channels operating, fpga logic active, i/os around serdes pins quiet, reference clock @ 10x mode.
3-37 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet table 3-9. serdes/pcs latency breakdown (parallel clock cycle) figure 3-13. transmitter and receiver block diagram item description min. average max. bypass transmit data latency t1 fpga bridge transmit 1351 t2 8b10b encoder 2221 t3 serdes bridge transmit 2221 t4 serializer 2.4 receive data latency r1 deserializer 1.2 r2 serdes bridge receive 2221 r3 w ord alignment 4440 r4 8b10b decoder 1111 r5 clock tolerance compensation 7 15 23 1 r6 fpga bridge receive 1351 hdoutpi hdoutni deserializer 1: 8 /1:10 polarity adjust elastic buffer fifo encoder serdes pcs bypass transmitter receiver recovered clock fpga receive clock fpga receive data transmit data cdr refclk hdinpi hdinni eq polarity adjust up sample fifo serdes brid g e fpga brid g e serializer 8 :1/10:1 wa dec fpga ebrd clock transmit clock tx pll refclk fpga core down sample fifo bypass bypass bypass bypass bypass bypass r1 r2 r3 r4 r5 r6 t1 t2 t3 t4 transmit clock
3-38 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet serdes high speed data receiver (latticeecp2m family only) table 3-10. serial input data speci?ations input data jitter tolerance a receivers ability to tolerate incoming signal jitter is very dependent on jitter type. high speed serial interface stan- dards have recognized the dependency on jitter type and have recently modi?d speci?ations to indicate toler- ance levels for different jitter types as they relate to speci? protocols (e.g. fc, etc.). sinusoidal jitter is considered to be a worst case jitter type. table 3-11. receiver total jitter tolerance speci?ation table 3-12. periodic receiver jitter tolerance speci?ation symbol description min. typ. max. units rx-cid s stream of nontransitions 1 (cid = consecutive identical digits) @ 10 -12 ber 7 @ 3.125 gbps 20 @ 1.25 gbps bits v rx-diff-s differential input sensitivity 100 mv, p-p v rx-in input levels 0 v ccrx + 0.3 v v rx-cm-dc input common mode range (dc coupled) 0.5 1.2 v v rx-cm-ac input common mode range (ac coupled) 3 0 1.5 v t rx-relock cdr re-lock time 2 3000 bits z rx-term input termination 50/75 ohm/high z 50 ohms rl rx-rl return loss (without package) 9 db 1. this is the number of bits allowed without a transition on the incoming data stream when using dc coupling. 2. this is the typical number of bit times to re-lock to a new phase or frequency within +/- 300 ppm, assuming 8b10b encoded dat a. 3. ac coupling is used to interface to lvpecl and lvds. description fre q uency condition min. typ. max. units deterministic 3.125 gbps 600 mv differential eye 0.54 ui, p-p random 600 mv differential eye 0.26 ui, p-p total 600 mv differential eye 0.80 ui, p-p deterministic 2.5 gbps 600 mv differential eye 0.61 ui, p-p random 600 mv differential eye 0.22 ui, p-p total 600 mv differential eye 0.81 ui, p-p deterministic 1.25 gbps 600 mv differential eye 0.53 ui, p-p random 600 mv differential eye 0.22 ui, p-p total 600 mv differential eye 0.80 ui, p-p deterministic 250 gbps 600 mv differential eye ui, p-p random 600 mv differential eye ui, p-p total 600 mv differential eye ui, p-p note: values are measured with prbs 2 7 -1, all channels operating, fpga logic active, i/os around serdes pins quiet, voltages are nomi- nal, room temperature. description fre q uency condition min. typ. max. units periodic 3.125 gbps 600 mv differential eye 0.20 ui, p-p periodic 2.5 gbps 600 mv differential eye 0.22 ui, p-p periodic 1.25 gbps 600 mv differential eye 0.20 ui, p-p periodic 250 gbps 600 mv differential eye ui, p-p note: values are measured with prbs 2 7 -1, all channels operating.
3-39 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet serdes external reference clock (latticeecp2m family only) the external reference clock selection and its interface are a critical part of system applications for this product. table 3-13 speci?s reference clock requirements, over the full range of operating conditions. figure 3-14. jitter transfer serdes power-down/power-up speci?ation table 3-14. power-down and power-up speci?ation table 3-13. external reference clock speci?ation (refclkp/refclkn) symbol description min. typ. max. units f ref frequency range 25 320 mhz f ref-ppm frequency tolerance -300 300 ppm v ref-in-se input swing, single-ended clock 1 100 1200 mv, p-p v ref-in input levels 0 v ccrx + 0.3 v v ref-cm-dc input common mode range (dc coupled) 0.5 1.2 v v ref-cm-ac input common mode range (ac coupled) 2 0 1.5 v d ref duty cycle 3 40 60 % t ref-r rise time (20% to 80%) 500 1000 ps t ref-f fall time (80% to 20%) 500 1000 ps z ref-in-term input termination 50/2k ohms c ref-in-cap input capacitance 4 1.5 pf 1. the signal swing for a single-ended input clock must be as large as the p-p differential swing of a differential input clock to get the same gain at the input receiver. lower swings for the clock may be possible, but will tend to increase jitter. 2. w hen ac coupled, the input common mode range is determined by: (min input level) + (peak-to-peak input swing)/2 (input common mode voltage) (max input level) - (peak-to-peak input swing)/2 3. measured at 50% amplitude. 4. input capacitance of 1.5pf is total capacitance, including both device and package. symbol description max. units t p w rdn power-down time after all power down register bits set to ? 10 s t p w rup power-up time after all power down register bits set to ? 5 ms frequency (mhz) db note: this graph is for a nominal device. -25.00 -20.00 -15.00 -10.00 -5.00 0.00 5.00 0.1 1 10 100 jitter t. gain@25?,1.20v, pj=100ps
3-40 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet pci express electrical and timing characteristics ac and dc characteristics table 3-15. transmit 1, 2 table 3-16. receive symbol description test conditions min typ max units ui unit interval 399.88 400 400.12 ps v tx-diff_p-p differential peak-to-peak output volt- age 0.8 1.0 1.2 v v tx-de-ratio de-emphasis differential output volt- age ratio 0 -3.5 -7.96 db v tx-cm-ac_p rms ac peak common-mode output voltage ?0 mv v tx-cm-dc-line-delta maximum common mode voltage delta between n and p channels 25 mv v tx-dc-cm tx dc common mode voltage 0 v ccob + 5% v i tx-short output short circuit current v tx-d+ =0.0v v tx-d- =0.0v 90 ma z tx-diff-dc differential output impedance 80 100 120 ohms t tx-rise tx output rise time 20 to 80% 0.125 ui t tx-fall tx output fall time 20 to 80% 0.125 ui l tx-ske w lane-to-lane static output skew for all lanes in port/link 1.3 ns t tx-eye transmitter eye width 0.75 ui t tx-eye-median-to-max-jitter 3 0.125 ui c tx ac coupling capacitor 75 200 nf 1. values are measured at 2.5 gbps. 2. compliant to pci express v1.1. 3. measured at 60ps with plug-in board and jitter due to socket removed. symbol description test conditions min. typ. max. units ui unit interval 399.88 400 400.12 ps v rx-diff_p-p differential peak-to-peak input voltage 0.175 v v rx-idle-det-diff_p-p idle detect threshold voltage 65 175 mv z rx-diff-dc dc differential input impedance 80 100 120 ohms z rx-dc dc input impedance 40 50 60 ohms z rx-high-imp-dc 1 power-down dc input impedance 200k ohms t rx-eye receiver eye width 0.4 ui t rx-eye-median-to-max-jitter 0.3 ui notes: 1. measured with external ac-coupling on the receiver 2. values are measured at 2.5 gbps
3-41 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet table 3-17. reference clock symbol description test conditions min. typ. max. units f refclk reference clock frequency 100 mhz v cm input common mode voltage 0.65 v t r /t f clock input rise/fall time 1.0 ns v s w differential input voltage swing 0.6 1.6 v dc refclk input clock duty cycle 40 50 60 % ppm reference clock tolerance -300 +300 ppm
3-42 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet latticeecp2/m sysconfig port timing speci?ations over recommended operating conditions parameter description min. max. units sysconfig byte data flow t sucbdi byte d[0:7] setup time to cclk 7 ns t hcbdi byte d[0:7] hold time to cclk 1 ns t codo cclk to dout in flowthrough mode 12 ns t sucs csn[0:1] setup time to cclk 7 ns t hcs csn[0:1] hold time to cclk 1 ns t su w d w rite signal setup time to cclk 7 ns t h w d w rite signal hold time to cclk 1 ns t dcb cclk to busy delay time 12 ns t cord cclk to out for read data 12 ns sysconfig byte slave clocking t bsch byte slave cclk minimum high pulse 6 ns t bscl byte slave cclk minimum low pulse 9 ns t bscyc byte slave cclk cycle time 15 ns sysconfig serial (bit) data flow t suscdi di setup time to cclk slave mode 7 ns t hscdi di hold time to cclk slave mode 1 ns t codo cclk to dout in flowthrough mode 12 ns t sumcdi di setup time to cclk master mode 7 ns t hmcdi di hold time to cclk master mode 1 ns sysconfig serial slave clocking t ssch serial slave cclk minimum high pulse 6 ns t sscl serial slave cclk minimum low pulse 6 ns sysconfig por, initialization and wake-up t icfg minimum vcc to initn high 50 ms t vmc time from t icfg to valid master cclk 2 us t prgmrj programn pin pulse rejection 8 ns t prgm programn low time to start con?uration 25 ns t dinit programn high to initn high delay 1 ms t dppinit delay time from programn low to initn low 37 ns t dppdone delay time from programn low to done low 37 ns t iodiss user i/o disable from programn low 35 ns t ioenss user i/o enabled time from cclk edge during w ake-up sequence 25 ns t m w c additional w ake master clock signals after done pin high 120 cycles sysconfig spi port t cfgx initn high to cclk low 1 s t csspi initn high to csspin low 2 us t cscclk cclk low before csspin low 0 ns t socdo cclk low to output valid 15 ns t soe csspin[0:1] active setup time 300 ns t cspid csspin[0:1] low to first cclk edge setup time 300+3cyc 600+6cyc ns
3-43 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet figure 3-15. sysconfig parallel port read cycle f maxspi max. cclk frequency - spi flash read opcode (0x03) (spifastn = 1) 20 mhz max. cclk frequency - spi flash fast read opcode (0x0b) (spifastn = 0) 50 mhz t suspi sospi data setup time before cclk 7 ns t hspi sospi data hold time after cclk 2 ns timing v.a 0.10 parameter min. max. units master clock frequency selected value - 30% selected value + 30% mhz duty cycle 40 60 % timing v.a 0.10 latticeecp2/m sysconfig port timing speci?ations (continued) over recommended operating conditions parameter description min. max. units cclk 1 cs1 n cs n write n busy d[0:7] t sucs t hcs t suwd t cord t dcb t hwd t bscyc t bsch t bscl 1. in master parallel mode the fpga pro v ides cclk. in sla v e parallel mode the external de v ice pro v ides cclk. byte 0 byte 1 byte 2 byte n
3-44 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet figure 3-16. sysconfig parallel port write cycle figure 3-17. sysconfig master serial port timing figure 3-18. sysconfig slave serial port timing cclk 1 cs1 n cs n write n busy d[0:7] t sucs t hcs t suwd t hcbdi t dcb t hwd t bscyc t bsch t bscl t sucbdi byte 0 byte 1 byte 2 byte n 1. in master parallel mode the fpga pro v ides cclk. in sla v e parallel mode the external de v ice pro v ides cclk. cclk (o u tp u t) di n dout t sumcdi t hmcdi t codo cclk (inp u t) di n dout t suscdi t hscdi t codo t sscl t ssch
3-45 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet figure 3-19. power-on-reset (por) timing figure 3-20. con?uration from programn timing cclk 2 do n e v cc / v ccaux 1 cfg[2:0] 3 t icfg v alid i n it n t v mc t sucfg t hcfg 1. time taken from v cc or v ccaux , w hiche v er is the last to reach its v mi n . 2. de v ice is in a master mode. 3. the cfg pins are normally static (hard w ired). do n e cclk cfg[2:0] 1 user i/o i n it n program n t prgmrj t di n it t dppi n it t di n itd t iodiss t sucfg t hcfg v alid 1. the cfg pins are normally static (hard w ired)
3-46 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet figure 3-21. wake-up timing figure 3-22. spi/spim con?uration waveforms cclk do n e program n user i/o i n it n t ioe n ss wake-up t mwc opcode address 0 1 2 3 ? 7 8 9 10 ? 31 32 33 34 ? 127 12 8 v cc program n do n e i n it n spifast n csspi0 n csspi1 n cclk sispi/busy spid0 capt u re cfgx and spifast n capt u re cr0 & cib ignore v alid bitstream
3-47 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet jtag port timing speci?ations over recommended operating conditions figure 3-23. jtag port timing waveforms symbol parameter min max units f max tck clock frequency 25 mhz t btcp tck [bscan] clock pulse width 40 ns t btcph tck [bscan] clock pulse width high 20 ns t btcpl tck [bscan] clock pulse width low 20 ns t bts tck [bscan] setup time 8 ns t bth tck [bscan] hold time 10 ns t btrf tck [bscan] rise/fall time 50 mv/ns t btco tap controller falling edge of clock to valid output 10 ns t btcodis tap controller falling edge of clock to valid disable 10 ns t btcoen tap controller falling edge of clock to valid enable 10 ns t btcrs bscan test capture register setup time 8 ns t btcrh bscan test capture register hold time 25 ns t butco bscan test update register, falling edge of clock to valid output 25 ns t btuodis bscan test update register, falling edge of clock to valid disable 25 ns t btupoen bscan test update register, falling edge of clock to valid enable 25 ns timing v.a 0.10 tms tdi tck tdo data to b e capt u red from i/o data to b e dri v en o u t to i/o a t a d d i l a v a t a d d i l a v a t a d d i l a v a t a d d i l a v data capt u red t btcph t btcpl t btcoe n t btcrs t btupoe n t butco t btuodis t btcrh t btco t btcodis t bts t bth t btcp
3-48 dc and switching characteristics lattice semiconductor latticeecp2/m family data sheet switching test conditions figure 3-24 shows the output test load that is used for ac testing. the speci? values for resistance, capacitance, voltage, and other test conditions are shown in table 3-18. figure 3-24. output test load, lvttl and lvcmos standards table 3-18. test fixture required components, non-terminated interfaces test condition r 1 r 2 c l timing ref. v t lvttl and other lvcmos settings (l -> h, h -> l) ? 0pf lvcmos 3.3 = 1.5v lvcmos 2.5 = v ccio /2 lvcmos 1.8 = v ccio /2 lvcmos 1.5 = v ccio /2 lvcmos 1.2 = v ccio /2 lvcmos 2.5 i/o (z -> h) 1m v ccio /2 lvcmos 2.5 i/o (z -> l) 1m v ccio /2 v ccio lvcmos 2.5 i/o (h -> z) 100 v oh - 0.10 lvcmos 2.5 i/o (l -> z) 100 v ol + 0.10 v ccio note: output test conditions for all other interfaces are determined by the respective standards. dut v t r1 r2 cl* test poi nt *cl includes test fixture and probe capacitance
www.latticesemi.com 4-1 ds1006 pinout information_01.4 july 2007 advance data sheet ds1006 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. signal descriptions signal name 1, 2, 3 i/o description general purpose p[edge] [row/column number*]_[a/b] i/o [edge] indicates the edge of the device on which the pad is located. valid edge designations are l (left), b (bottom), r (right), t (top). [row/column number] indicates the pfu row or the column of the device on which the pic exists. w hen edge is t (top) or b (bottom), only need to spec- ify row number. w hen edge is l (left) or r (right), only need to specify col- umn number. [a/b] indicates the pio within the pic to which the pad is connected. some of these user-programmable pins are shared with special function pins. these pins, when not used as special purpose pins, can be programmed as i/os for user logic. during con?uration the user-programmable i/os are tri-stated with an internal pull-up resistor enabled. if any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after con?uration. gsrn i global reset signal (active low). any i/o pin can be gsrn. nc no connect. gnd ground. dedicated pins. v cc power supply pins for core logic. dedicated pins. v ccaux auxiliary power supply pin. this dedicated pin powers all the differential and referenced input buffers. v cciox dedicated power supply pins for i/o bank x. v ref1_x , v ref2_x reference supply pins for i/o bank x. pre-determined pins in each bank are assigned as v ref inputs. w hen not used, they may be used as i/o pins. xres 4 10k ohm +/-1% resistor must be connected between this pad and ground. pllcap 4 external capacitor connection for pll. pll, dll and clock functions (used as user programmable i/o pins when not in use for pll or clock pins) [loc][num]_v ccpll power supply pin for pll: ulm, llm, urm, lrm, num = row from center. [loc][num]_gpll[t, c]_in_a i general purpose pll (gpll) input pads: ulm, llm, urm, lrm, num = row from center, t = true and c = complement, index a,b,c...at each side. [loc][num]_gpll[t, c]_fb_a i optional feedback gpll input pads: ulm, llm, urm, lrm, num = row from center, t = true and c = complement, index a,b,c...at each side. [loc][num]_spll[t, c]_in_a i secondary pll (spll) input pads: ulm, llm, urm, lrm, num = row from center, t = true and c = complement, index a,b,c...at each side. [loc][num]_spll[t, c]_fb_a i optional feedback (spll) input pads: ulm, llm, urm, lrm, num = row from center, t = true and c = complement, index a,b,c...at each side. [loc][num]_dll[t, c]_in_a i dll input pads: ulm, llm, urm, lrm, num = row from center, t = true and c = complement, index a,b,c...at each side. [loc][num]_dll[t, c]_fb_a i optional feedback (dll) input pads: ulm, llm, urm, lrm, num = row from center, t = true and c = complement, index a,b,c...at each side. pclk[t, c]_[n:0]_[3:0] i primary clock pads, t = true and c = complement, n per side, indexed by bank and 0,1,2,3 within bank. [loc]dqs[num] i dqs input pads: t (top), r (right), b (bottom), l (left), dqs, num = ball function number. any pad can be con?ured to be output. latticeecp2/m family data sheet pinout information
4-2 pinout information lattice semiconductor latticeecp2/m family data sheet test and programming (dedicated pins) tms i test mode select input, used to control the 1149.1 state machine. pull-up is enabled during con?uration. tck i test clock input pin, used to clock the 1149.1 state machine. no pull-up enabled. tdi i test data in pin. used to load data into device using 1149.1 state machine. after power-up, this tap port can be activated for con?uration by sending appropriate command. (note: once a con?uration port is selected it is locked. another con?uration port cannot be selected until the power-up sequence). pull-up is enabled during con?uration. tdo o output pin. test data out pin used to shift data out of a device using 1149.1. vccj power supply pin for jtag test access port. con?uration pads (used during sysconfig) cfg[2:0] i mode pins used to specify con?uration mode values latched on rising edge of initn. during con?uration, a pull-up is enabled. these are dedicated pins. initn i/o open drain pin. indicates the fpga is ready to be con?ured. during con?- uration, a pull-up is enabled. it is a dedicated pin. programn i initiates con?uration sequence when asserted low. this pin always has an active pull-up. this is a dedicated pin. done i/o open drain pin. indicates that the con?uration sequence is complete, and the startup sequence is in progress. this is a dedicated pin. cclk i/o con?uration clock for con?uring an fpga in sysconfig mode. busy/sispi i/o read control command in spi3 or spix mode. csn i sysconfig chip select (active low). during con?uration, a pull-up is enabled. cs1n i sysconfig chip select (active low). during con?uration, a pull-up is enabled. w riten i w rite data on parallel port (active low). d[7:0]/spid[0:7] i/o sysconfig port data i/o. dout/cson (for latticeecp2 only) dout/cson/csspi1n (for latticeecp2m) o output for serial con?uration data (rising edge of cclk) when using sysconfig port. csspi1n is used in spim mode only. di/csspi0n i/o input for serial con?uration data (clocked with cclk) when using syscon- fig port. during con?uration, a pull-up is enabled. output when used in spi/ spim modes. dedicated serdes signals [loc]_sq_vccaux33 termination resistor switching power (3.3v). this pin must be tied to 3.3v even if the quad is unused. [loc]_sq_refclkn i negative reference clock input [loc]_sq_refclkp i positive reference clock input [loc]_sq_vccp pll and reference clock buffer power (1.2v). this pin must be tied to 1.2v even if the quad is unused. [loc]_sq_vccibm input buffer power supply, channel m (1.2v/1.5v). this pin should be left ?at- ing if the channel is unused. [loc]_sq_vccobm output buffer power supply, channel m (1.2v/1.5v). this pin should be left ?ating if the channel is unused. [loc]_sq_hdoutnm o high-speed output, negative channel m [loc]_sq_hdoutpm o high-speed output, positive channel m [loc]_sq_hdinnm i high-speed input, negative channel m signal descriptions (cont.) signal name 1, 2, 3 i/o description
4-3 pinout information lattice semiconductor latticeecp2/m family data sheet [loc]_sq_hdinpm i high-speed input, positive channel m [loc]_sq_vcctxm 4 transmitter power supply, channel m (1.2v). this pin must be tied to 1.2v even if the channel is unused. [loc]_sq_vccrxm 4 receiver power supply, channel m (1.2v). this pin must be tied to 1.2v even if the channel is unused. 1. these signals are relevant for latticeecp2m family. 2. m de?es the associated channel in the quad. 3. these signals are de?ed in quads [loc] indicates the corner serdes quad is located: ulc (upper left), urc (upper right), llc (lower left), lrc (lower right). 4. w hen placing switching i/os around these critical pins that are designed to supply the device with the proper reference or suppl y voltage, care must be given. for more information, refer to technical note tn1159, latticeecp2/m pin assignment recommendations . signal descriptions (cont.) signal name 1, 2, 3 i/o description
4-4 pinout information lattice semiconductor latticeecp2/m family data sheet pics and ddr data (dq) pins associated with the ddr strobe (dqs) pin pics associated with dqs strobe pio within pic ddr strobe (dqs) and data (dq) pins for left and right edges of the device p[edge] [n-4] a dq b dq p[edge] [n-3] a dq b dq p[edge] [n-2] a dq b dq p[edge] [n-1] adq b dq p[edge] [n] a [edge]dqsn b dq p[edge] [n+1] a dq b dq p[edge] [n+2] a dq b dq p[edge] [n+3] a dq b dq for bottom edge of the device p[edge] [n-4] a dq b dq p[edge] [n-3] a dq b dq p[edge] [n-2] a dq b dq p[edge] [n-1] a dq b dq p[edge] [n] a [edge]dqsn b dq p[edge] [n+1] a dq b dq p[edge] [n+2] a dq b dq p[edge] [n+3] a dq b dq p[edge] [n+4] a dq b dq notes: 1. ? is a row pic number. 2. the ddr interface is designed for memories that support one dqs strobe up to 15 bits of data for the left and right edges and up to 17 bits of data for the bottom edge. in some packages, all the potential ddr data (dq) pins may not be available. pic numbering de?itions are provided in the ?ignal names column of the signal descriptions table.
4-5 pinout information lattice semiconductor latticeecp2/m family data sheet latticeecp2 pin information summary, lfe2-6 and lfe2-12 pin type lfe2-6 lfe2-12 144 tqfp 256 fpbga 144 tqfp 208 pqfp 256 fpbga 484 fpbga single ended user i/o 90 190 93 131 193 297 differential pair user i/o 43 95 45 62 96 148 con?uration tap pins 555555 muxed pins 14 14 14 14 14 14 dedicated pins (non tap) 777777 non con?uration muxed pins 34 54 33 40 54 57 dedicated pins 333333 vcc 1071014716 vccaux 4448416 vccpll 000000 vccio bank0 121224 bank1 121224 bank2 121224 bank3 121224 bank4 121224 bank5 121224 bank6 121224 bank7 121224 bank8 111212 gnd, gnd0 to gnd7 12 20 12 22 20 60 nc 4310044 single ended/ differential i/o pairs per bank (including emulated with resistors) bank0 8/4 18/6 8/4 18/9 18/9 50/25 bank1 17/8 34/17 18/9 18/9 34/17 46/23 bank2 4/2 20/10 4/2 11/5 20/10 24/12 bank3 8/4 12/6 8/4 11/5 12/6 16/8 bank4 18/9 32/16 18/9 19/9 32/16 46/23 bank5 8/4 14/7 10/5 18/9 17/8 46/23 bank6 9/4 26/13 9/4 18/8 26/13 32/16 bank7 12/6 20/10 12/6 12/6 20/10 23/11 bank8 6/2 14/7 6/2 6/2 14/7 14/7 true lvds i/o pairs per bank bank0 (top edge) 000000 bank1 (top edge) 000000 bank2 (right edge) 151456 bank3 (right edge) 333334 bank4 (bottom edge) 000000 bank5 (bottom edge) 000000 bank6 (left edge) 272678 bank7 (left edge) 555555 bank8 (right edge) 000000
4-6 pinout information lattice semiconductor latticeecp2/m family data sheet available ddr-interfaces per i/o bank 1 bank0 000000 bank1 000000 bank2 010011 bank3 000000 bank4 020023 bank5 010013 bank6 010011 bank7 010011 bank8 000000 pci capable i/os per bank bank0 000000 bank1 000000 bank2 000000 bank3 000000 bank4 18 32 18 19 32 46 bank5 8 14 10 18 17 46 bank6 000000 bank7 000000 bank8 000000 1. minimum requirement to implement a fully functional 8-bit wide ddr bus. available ddr interface consists of at least 12 i/os (1 dqs + 1 dqsb + 8 dqs + 1 dm + bank vref1). latticeecp2 pin information summary, lfe2-6 and lfe2-12 (cont.) pin type lfe2-6 lfe2-12 144 tqfp 256 fpbga 144 tqfp 208 pqfp 256 fpbga 484 fpbga
4-7 pinout information lattice semiconductor latticeecp2/m family data sheet latticeecp2 pin information summary, lfe2-20 and lfe2-35 pin type lfe2-20 lfe2-35 208 pqfp 256 fpbga 484 fpbga 672 fpbga 484 fpbga 672 fpbga single ended user i/o 131 193 331 402 331 450 differential pair user i/o 62 96 165 200 165 224 con?uration tap pins 555555 muxed pins 14 14 14 14 14 14 dedicated pins (non tap) 777777 non con?uration muxed pins 42 54 60 64 60 68 dedicated pins 333333 vcc 14 7 18241622 vccaux 8 4 16 16 16 16 vccpll 000022 vccio bank0 224545 bank1 224545 bank2 224545 bank3 224545 bank4 224545 bank5 224545 bank6 224545 bank7 224545 bank8 212222 gnd, gnd0 to gnd7 22 20 60 72 60 72 nc 0 1 8 101 8 102 single ended/ differential i/o pairs per bank (including emulated with resistors) bank0 18/9 18/9 50/25 67/33 50/25 67/33 bank1 18/9 34/17 46/23 52/26 46/23 52/26 bank2 11/5 20/10 34/17 36/18 34/17 48/24 bank3 11/5 12/6 22/11 32/16 22/11 42/21 bank4 19/9 32/16 46/23 50/25 46/23 54/27 bank5 18/9 17/8 46/23 68/34 46/23 68/34 bank6 18/8 26/13 40/20 48/24 40/20 58/29 bank7 12/6 20/10 33/16 35/17 33/16 47/23 bank8 6/2 14/7 14/7 14/7 14/7 14/7 true lvds i/o pairs per bank bank0 (top edge) 000000 bank1 (top edge) 000000 bank2 (right edge) 4599912 bank3 (right edge) 335859 bank4 (bottom edge) 000000 bank5 (bottom edge) 000000 bank6 (left edge) 6 7 10 12 10 13 bank7 (left edge) 5588811 bank8 (right edge) 000000
4-8 pinout information lattice semiconductor latticeecp2/m family data sheet available ddr-interfaces per i/o bank 1 bank0 000000 bank1 000000 bank2 012223 bank3 000202 bank4 023333 bank5 013434 bank6 012313 bank7 012223 bank8 000000 pci capable i/os per bank bank0 000000 bank1 000000 bank2 000000 bank3 000000 bank4 19 32 46 50 46 54 bank5 18 17 46 68 46 68 bank6 000000 bank7 000000 bank8 000000 1. minimum requirement to implement a fully functional 8-bit wide ddr bus. available ddr interface consists of at least 12 i/os (1 dqs + 1 dqsb + 8 dqs + 1 dm + bank vref1). latticeecp2 pin information summary, lfe2-20 and lfe2-35 (cont.) pin type lfe2-20 lfe2-35 208 pqfp 256 fpbga 484 fpbga 672 fpbga 484 fpbga 672 fpbga
4-9 pinout information lattice semiconductor latticeecp2/m family data sheet latticeecp2 pin information summary, lfe2-50 and lfe2-70 pin type lfe2-50 lfe2-70 484 fpbga 672 fpbga 672 fpbga 900 fpbga single ended user i/o 339 500 500 583 differential pair user i/o 169 249 249 290 con?uration tap pins 5555 muxed pins 14 14 14 14 dedicated pins (non tap) 7777 non con?uration muxed pins 68 79 79 89 dedicated pins 3333 vcc 16 20 20 26 vccaux 16 16 16 17 vccpll 4424 vccio bank0 4556 bank1 4556 bank2 4556 bank3 4556 bank4 4556 bank5 4556 bank6 4556 bank7 4556 bank8 2222 gnd, gnd0 to gnd7 61 72 72 104 nc 0 3 5 101 single ended/ differential i/o pairs per bank (including emulated with resistors) bank0 50/25 67/33 67/33 84/42 bank1 46/23 66/33 66/33 76/38 bank2 38/19 56/28 56/28 74/37 bank3 22/11 48/24 48/24 48/24 bank4 46/23 62/31 62/31 72/35 bank5 46/23 68/34 68/34 80/40 bank6 40/20 64/32 64/32 64/32 bank7 37/18 55/27 55/27 71/35 bank8 14/7 14/7 14/7 14/7 true lvds i/o pairs per bank bank0 (top edge) 0000 bank1 (top edge) 0000 bank2 (right edge) 9 13 13 18 bank3 (right edge) 5 12 12 12 bank4 (bottom edge) 0000 bank5 (bottom edge) 0000 bank6 (left edge) 10 16 16 16 bank7 (left edge) 8 12 12 16 bank8 (right edge) 0000
4-10 pinout information lattice semiconductor latticeecp2/m family data sheet available ddr-interfaces per i/o bank 1 bank0 0000 bank1 0000 bank2 2334 bank3 0333 bank4 3444 bank5 3445 bank6 1444 bank7 2334 bank8 0000 pci capable i/os per bank bank0 0000 bank1 0000 bank2 0000 bank3 0000 bank4 46 62 62 72 bank5 46 68 68 80 bank6 0000 bank7 0000 bank8 0000 1. minimum requirement to implement a fully functional 8-bit wide ddr bus. available ddr interface consists of at least 12 i/os (1 dqs + 1 dqsb + 8 dqs + 1 dm + bank vref1). latticeecp2 pin information summary, lfe2-50 and lfe2-70 (cont.) pin type lfe2-50 lfe2-70 484 fpbga 672 fpbga 672 fpbga 900 fpbga
4-11 pinout information lattice semiconductor latticeecp2/m family data sheet latticeecp2m pin information summary pin type lfe2m20 lfe2m35 256 fpbga 484 fpbga 256 fpbga 484 fpbga 672 fpbga single ended user i/o 140 304 140 303 410 differential pair user i/o 70 152 70 151 199 con?uration tap pins 55555 muxed pins 14 14 14 14 14 dedicated pins (non tap) 77777 non con?uration muxed pins 64 84 60 84 89 dedicated pins 33333 vcc 61661629 vccaux 484817 vccpll 14148 vccio bank0 14145 bank1 13134 bank2 24245 bank3 24245 bank4 24244 bank5 24245 bank6 24245 bank7 24245 bank8 12122 gnd, gnd0 to gnd7 22 57 22 57 80 nc 17 11 17 12 37 single ended/ differential i/o pairs per bank (including emulated with resistors) bank0 0/0 36/18 0/0 36/18 63/31 bank1 0/0 18/9 0/0 18/9 18/9 bank2 14/7 30/15 14/7 30/15 50/25 bank3 16/8 36/18 16/8 36/18 43/21 bank4 32/16 62/31 32/16 62/31 50/21 bank5 20/10 28/14 20/10 28/14 60/30 bank6 16/8 40/20 16/8 39/19 52/25 bank7 28/14 40/20 28/14 40/20 60/30 bank8 14/7 14/7 14/7 14/7 14/7 true lvds i/o pairs per bank bank0 (top edge) 00000 bank1 (top edge) 00000 bank2 (right edge) 373712 bank3 (right edge) 494911 bank4 (bottom edge) 00000 bank5 (bottom edge) 00000 bank6 (left edge) 4 10 4 10 14 bank7 (left edge) 7 10 7 10 15 bank8 (right edge) 00000
4-12 pinout information lattice semiconductor latticeecp2/m family data sheet available ddr-interfaces per i/o bank 1 bank0 00000 bank1 00000 bank2 02013 bank3 04002 bank4 24243 bank5 12123 bank6 03012 bank7 12123 bank8 0 0 0 11 16 pci capable i/os per bank bank0 00000 bank1 00000 bank2 00000 bank3 00000 bank4 32 62 32 62 50 bank5 20 28 20 28 60 bank6 16 40 16 39 52 bank7 28 40 28 40 60 bank8 00000 1. minimum requirement to implement a fully functional 8-bit wide ddr bus. available ddr interface consists of at least 12 i/os (1 dqs + 1 dqsb + 8 dqs + 1 dm + bank vref1). latticeecp2m pin information summary (cont.) pin type lfe2m20 lfe2m35 256 fpbga 484 fpbga 256 fpbga 484 fpbga 672 fpbga
4-13 pinout information lattice semiconductor latticeecp2/m family data sheet available device resources by package, latticeecp2 available device resources by package, latticeecp2m resource device 256 fpbga 484 fpbga 672 fpbga 900 fpbga pll/dll ecp2-6 4 ecp2-12 4 4 ecp2-20 4 4 4 ecp2-35 4 4 ecp2-50 6 6 ecp2-70 8 8 resource device 256 fpbga 484 fpbga 672 fpbga 900 fpbga 1152 fpbga 1156 fpbga pll/dll ecp2m20 10 10 ecp2m35 10 10 10 ecp2m50 10 10 10 ecp2m70 10 10 ecp2m100 10 10 10
4-14 pinout information lattice semiconductor latticeecp2/m family data sheet latticeecp2 power supply and nc signals 144 tqfp 3 208 pqfp 3 256 fpbga 4 484 fpbga 4 vcc 16, 22, 29, 48, 54, 83, 94, 102, 128, 135 12, 19, 28, 40, 74, 80, 97, 116, 129, 140, 146, 171, 188, 198 lfe2-6: g7, g9, g10, h7, j10, k10, k8 lfe2-12/lfe2-20: g7, g9, g10, h7, j10, k10, k8 lfe2-12/lfe2-20: n6, n18, j10, j11, j12, j13, k14, k9, l14, l9, m14, m9, n14, n9, p10, p11, p12, p13 lfe2-35/lfe2-50: j10, j11, j12, j13, k14, k9, l14, l9, m14, m9, n14, n9, p10, p11, p12, p13 vccio0 139 195, 206 c5, e7 g10, g9, h8, h9 vccio1 117 162, 170 c12, e10 g11, g12, g13, g14 vccio2 106 143, 148 e14, g12 h14, h15, j15, k16 vccio3 89 123, 135 k12, m14 l16, m16, n16, p16 vccio4 64 93, 100 m10, p12 r14, t12, t13, t14 vccio5 42 55, 63 m7, p5 r9, t10, t11, t9 vccio6 31 38, 44 k5, m3 n7, p7, p8, r8 vccio7 9 10, 14 e3, g5 j8, k7, l7, m7 vccio8 85 113, 118 t15 p15, r15 vccj 35 51 k7 t8 vccaux 6, 39, 90, 142 7, 30, 70, 86, 125, 151, 174, 190 g8, h10, j7, k9 g5, k5, r5, v7, v11, v8, v13, v15, m17, p17, e17, g18, d11, f13, c5, e6 vccpll none none none lfe2-12/lfe2-20: none lfe2-35: n6, n18 lfe2-50: n6, n18, k6, j16 gnd 1 11, 21, 30, 47, 51, 61, 81, 95, 105, 120, 133, 138 5, 13, 17, 25, 32, 42, 60, 68, 77, 81, 89, 102, 115, 122, 139, 145, 159, 169, 175, 184, 192, 201 a1, a16, b12, b5, c8, e15, e2, h14, h8, h9, j3, j8, j9, m15, m2, p9, r12, r5, t1, t16 a22, aa19, aa4, ab1, ab22, b19, b4, c14, c9, d2, d21, f17, f6, h10, h11, h12, h13, j14, j20, j3, j9, k10, k11, k12, k13, k15, k8, l10, l11, l12, l13, l15, l8, m10, m11, m12, m13, m15, m8, n10, n11, n12, n13, n15, n8, p14, p20, p3, p9, r10, r11, r12, r13, u17, u6, w 2, w 21, y14, y9, a1 nc 2 lfe2-6: 45, 46, 124, 127 lfe2-12: 127 none lfe2-6: k6, r3, p4 lfe2-12/lfe2-20: none lfe2-12: e3, f3, f1, h4, f2, h5, g1, g3, g2, g4, k6, n1, m2, n2, m1, n3, n5, n4, p5, n19, m19, j22, l22, h22, k22, j16, d22, f21, e21, e22, h19, g20, g19, f20, c21, c22, h6, j6, h3, h2, h17, h16, h20, h18 lfe2-20/lfe2-35: k6, j16, h6, j6, h3, h2, h17, h16, h20, h18 lfe2-50: none 1. all grounds must be electrically connected at the board level. for fpbga packages, the total number of gnd balls is less tha n the actual number of gnd logic connections from the die to the common package gnd plane. 2. nc pins should not be connected to any active signals, vcc or gnd. 3. pin orientation follows the conventional order from the pin 1 marking of the top side view and counter-clockwise. 4. pin orientation a1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and nu merical order ascending horizontally.
4-15 pinout information lattice semiconductor latticeecp2/m family data sheet latticeecp2 power supply and nc (cont.) signals 672 fpbga 3 900 fpbga 3 vcc lfe2-20: r8, p18, m8, l20, l12, l13, l14, l15, m11, m12, m15, m16, n11, n16, p11, p16, r11, r12, r15, r16, t12, t13, t14, t15 lfe2-35/lfe2-50: l12, l13, l14, l15, m11, m12, m15, m16, n11, n16, p11, p16, r11, r12, r15, r16, t12, t13, t14, t15 lfe2-70: l12, l13, l14, l15, m11, m12, m15, m16, n11, n16, p11, p16, r11, r12, r15, r16, t12, t13, t14, t15 aa11, aa20, k11, k21, k22, l11, l12, l13, l18, l19, l20, m11, m20, n11, n20, v11, v20, w 11, w 20, y10, y11, y12, y13, y18, y19, y20 vccio0 d11, d6, g9, j12, k12 j13, j14, k12, k13, k14, k15 vccio1 d16, d21, g18, j15, k15 j17, j18, j20, k17, k18, k20 vccio2 f23, j20, l23, m17, m18 l21, m21, m22, n21, n22, r21 vccio3 aa23, r17, r18, t23, v20 u21, u22, v21, v22, w 21, y22 vccio4 ac16, ac21, u15, v15, y18 aa16, aa17, aa18, aa19, ab17, ab18 vccio5 ac11, ac6, u12, v12, y9 aa12, aa13, aa14, ab12, ab13, ab14 vccio6 aa4, r10, r9, t4, v7 u10, u9, v10, w 10, w 9, y9 vccio7 f4, j7, l4, m10, m9 l10, l9, m10, n10, p10, r10 vccio8 ae25, v18 aa21, y21 vccj ab5 ad3 vccaux j10, j11, j16, j17, k18, l18, t18, u18, v16, v17, v10, v11, t9, u9, k9, l9 aa15, ab11, ab19, ab20, j11, j12, j19, k19, l22, m9, n9, p21, p9, t10, t21, v9, w 22 vccpll lfe2-20: none lfe2-35/lfe2-70: r8, p18 lfe2-50: r8, p18, m8, l20 p22, p8, t22, y7 gnd 1 a2, a25, aa18, aa24, aa3, aa9, ad11, ad16, ad21, ad6, ae1, ae26, af2, af25, b1, b26, c11, c16, c21, c6, f18, f24, f3, f9, j13, j14, j21, j6, k10, k11, k13, k14, k16, k17, l10, l11, l16, l17, l24, l3, m13, m14, n10, n12, n13, n14, n15, n17, p10, p12, p13, p14, p15, p17, r13, r14, t10, t11, t16, t17, t24, t3, u10, u11, u13, u14, u16, u17, v13, v14, v21, v6 a1, a30, ac28, ac3, ah13, ah18, ah23, ah28, ah3, ah8, ak1, ak30, c13, c18, c23, c28, c3, c8, h28, h3, l14, l15, l16, l17, m12, m13, m14, m15, m16, m17, m18, m19, n12, n13, n14, n15, n16, n17, n18, n19, n28, n3, p11, p12, p13, p14, p15, p16, p17, p18, p19, p20, r11, r12, r13, r14, r15, r16, r17, r18, r19, r20, t11, t12, t13, t14, t15, t16, t17, t18, t19, t20, u11, u12, u13, u14, u15, u16, u17, u18, u19, u20, v12, v13, v14, v15, v16, v17, v18, v19, v28, v3, w 12, w 13, w 14, w 15, w 16, w 17, w 18, w 19, y14, y15, y16, y17 nc 2 lfe2-20: e4, e3, e2, e1, h6, h5, f2, f1, h8, j9, g4, g3, k3, k2, k1, l2, l1, m2, m1, n2, t1, t2, p8, p6, p5, p4, u1, v1, p3, r3, r4, u2, v2, w 2, t6, r5, aa19, w 17, y19, y17, af20, ae20, aa20, w 18, ad20, ae21, af21, af22, r22, t21, p26, p25, r24, r23, p20, r19, p21, p19, p23, p22, n22, r21, n26, n25, j26, j25, j23, k23, h26, h25, h24, h23, f22, e24, d25, c25, d24, b25, h21, g22, b24, c24, d23, c23, e19, c19, b21, b20, d19, b19, g17, e18, g19, f17, a20, a19, e17, d18, m3, n6, p24 lfe2-35: k3, k2, k1, l2, l1, m2, m1, n2, m8, p3, r3, r4, u2, v2, w 2, af20, ae20, aa20, w 18, ad20, ae21, af21, af22, p26, p25, r24, r23, p20, r19, l20, j26, j25, j23, k23, h26, h25, h24, h23, e19, c19, b21, b20, d19, b19, g17, e18, g19, f17, a20, a19, e17, d18, m3, n6, p24 lfe2-50: n6, p24, m3 lfe2-70: m8, l20, m3, p24, n6 a2, a3, a4, a5, ab28, ac4, ad23, ae1, ae2, ae29, ae3, ae30, ae4, ae5, ae6, af1, af2, af23, af26, af27, af28, af29, af3, af30, af4, af5, ag1, ag13, ag16, ag18, ag2, ag26, ag27, ag28, ag29, ag3, ag30, ag4, ag8, ah1, ah16, ah2, ah26, ah27, ah29, ah30, ah4, aj1, aj2, aj27, aj28, aj29, aj3, aj30, ak2, ak27, ak28, ak29, ak3, b1, b2, b3, b30, b4, b5, c1, c2, c29, c30, c4, d13, d18, d23, d28, d29, d3, d30, d4, e25, e26, e27, e28, e29, e3, e30, e4, e5, e6, f25, f5, f6, g6, g7, k10, k9, n27, n4, r1, r2, v27, v4 1. all grounds must be electrically connected at the board level. for fpbga packages, the total number of gnd balls is less tha n the actual number of gnd logic connections from the die to the common package gnd plane. 2. nc pins should not be connected to any active signals, vcc or gnd. 3. pin orientation a1 starts from the upper left corner of the top side view with alphabetical order ascending vertically and nu merical order ascending horizontally.
4-16 pinout information lattice semiconductor latticeecp2/m family data sheet latticeecp2m power supply and nc signal 256 fpbga 484 fpbga 672 fpbga v cc g7, g9, h7, j10, k10, k8 j10, j11, j12, j13, k14, k9, l14, l9, m14, m9, n14, n9, p10, p11, p12, p13 lfe2m35: ad13, ad14, ad16, ad17, ad19, ad21, ad22, ad24, ad25, l12, l13, l14, l15, m11, m12, m15, m16, n11, n16, p11, p16, r11, r12, r15, r16, t12, t13, t14, t15 v ccio0 e7 b5, b9, e7, h9 b12, b7, f11, j13, k12 v ccio1 e10 d13, e16, h14 d18, f16, j14, k15 v ccio2 e14, g12 e21, g18, j15, k19 g25, l21, m17, m25, n18 v ccio3 k12, m14 n19, p15, t18, v21 p18, r17, r25, t21, y25 v ccio4 m10, p12 aa18, r14, v16, w 13 aa16, ac18, u15, v14 v ccio5 m7, p5 aa5, r9, v7, w 10 aa11, ae12, ae7, u12, v13 v ccio6 k5, m3 n4, p8, t5, v2 p9, r10, r2, t6, y2 v ccio7 e3, g5 e2, g5, j8, k4 g2, l6, m10, m2, n9 v ccio8 t15 aa22, u19 ac24, u17 v ccj k7 w 4 aa7 v ccaux g8, h10, j7, k9 h11, h12, l15, l8, m15, m8, r11, r12 lfe2m35: ae19, j11, j12, j15, j16, l18, l9, m18, m9, r18, r9, t18, t9, v11, v12, v15, v16 v ccpll g10 r8, h15, h8, r15 h7, k6, p7, r8, v18, p20, j17, g19 serdes power 3 c15, b15, c12, a12, c11, c10, c14, c13, b9, c9, c5, c4, c8, c7, a6, c6, b3, c3 c22, b22, c19, a19, c18, c17, c21, c20, b16, c16, c12, c11, c15, c14, a13, c13, b10, c10 lfe2m35: c25, b25, c22, a22, c21, c20, c24, c23, b19, c19, c15, c14, c18, c17, a16, c16, b13, c13 gnd 1 a1, a15, a16, a3, a9, b12, b6, e15, e2, h14, h8, h9, j3, j8, j9, m15, m2, p9, r12, r5, t1, t16 a1, a10, a16, a22, aa19, aa4, ab1, ab22, b13, b19, b4, d16, d2, d21, d7, g19, g4, h10, h13, j14, j9, k10, k11, k12, k13, k15, k20, k3, k8, l10, l11, l12, l13, m10, m11, m12, m13, n10, n11, n12, n13, n15, n20, n3, n8, p14, p9, r10, r13, t19, t4, w 16, w 2, w 21, w 7, y10, y13 a13, a19, a2, a25, aa2, aa25, ab18, ab22, ab5, ab9, ae1, ae11, ae16, ae22, ae26, ae6, af13, af19, af2, af25, b1, b11, b16, b22, b26, b6, e18, e22, e5, e9, f2, f25, g11, g16, j22, j5, k11, k13, k14, k16, l10, l11, l16, l17, l2, l20, l25, l7, m13, m14, n10, n12, n13, n14, n15, n17, p10, p12, p13, p14, p15, p17, r13, r14, t10, t11, t16, t17, t2, t20, t25, t7, u11, u13, u14, u16, v22, v5, y11, y16 nc 2 d10, d11, d12, d13, d14, d4, d5, d6, d7, e11, e6, e8, e9, f10, f7, f8, f9 lfe2m20: d14, d15, e14, e15, f13, f14, f15, g12, g13, g14, g15 lfe2m35: ab3, ab4, ac1, ac2, ad15, ad18, ad20, ad23, ae13, ae25, af16, af22, b4, b5, c26, d20, d21, d22, d23, d24, d25, d26, e20, e21, e25, e26, f20, g20, k10, k17, r4, u10, u23, v10, w 7, n7, v7 1. all grounds must be electrically connected at the board level. for fpbga packages, the total number of gnd balls is less than the actual number of gnd logic connections from the die to the common package gnd plane. 2. nc pins should not be connected to any active signals, vcc or gnd. 3. for package migration across device densities, the designer must comprehend the package pin requirements for the serdes bloc ks. spe- ci?ally, the serdes power pins of the largest density device must be accounted to accommodate migration to other smaller devic es using the same package. please refer to technical note tn1160, latticeecp2/m density migration, for more details.
4-17 pinout information lattice semiconductor latticeecp2/m family data sheet lfe2-6e/6se and lfe2-12e/12se logic signal connections: 144 tqfp lfe2-6e/6-se lfe2-12e/12se pin number pin function bank dual function differential pin number pin function bank dual function differential 1 pl2a 7 vref2_7 t (lvds)* 1 pl2a 7 vref2_7 t (lvds)* 2 pl2b 7 vref1_7 c (lvds)* 2 pl2b 7 vref1_7 c (lvds)* 3 pl4a 7 t (lvds)* 3 pl4a 7 t (lvds)* 4 pl4b 7 c (lvds)* 4 pl4b 7 c (lvds)* 5 pl6a 7 t (lvds)* 5 pl6a 7 t (lvds)* 6 vccaux - 6 vccaux - 7 pl6b 7 c (lvds)* 7 pl6b 7 c (lvds)* 8 pl8a 7 t (lvds)* 8 pl8a 7 t (lvds)* 9 vccio7 7 9 vccio7 7 10 pl8b 7 c (lvds)* 10 pl8b 7 c (lvds)* 11 gnd - 11 gnd - 12 pl12a 7 t (lvds)* 12 pl12a 7 t (lvds)* 13 pl12b 7 c (lvds)* 13 pl12b 7 c (lvds)* 14 pl13a 7 pclkt7_0 t 14 pl13a 7 pclkt7_0 t 15 pl13b 7 pclkc7_0 c 15 pl13b 7 pclkc7_0 c 16 vcc - 16 vcc - 17 pl15a 6 pclkt6_0 t (lvds)* 17 pl15a 6 pclkt6_0 t (lvds)* 18 pl15b 6 pclkc6_0 c (lvds)* 18 pl15b 6 pclkc6_0 c (lvds)* 19 pl16a 6 vref2_6 t 19 pl16a 6 vref2_6 t 20 pl16b 6 vref1_6 c 20 pl16b 6 vref1_6 c 21 gnd - 21 gnd - 22 vcc - 22 vcc - 23 pl18a 6 llm0_gdllt_fb_a t 23 pl18a 6 llm0_gdllt_fb_a t 24 pl18b 6 llm0_gdllc_fb_a c 24 pl18b 6 llm0_gdllc_fb_a c 25 llm0_pllcap 6 25 llm0_pllcap 6 26 pl20a 6 llm0_gpllt_in_a** t (lvds)* 26 pl20a 6 llm0_gpllt_in_a** t (lvds)* 27 pl20b 6 llm0_gpllc_in_a** c (lvds)* 27 pl20b 6 llm0_gpllc_in_a** c (lvds)* 28 pl22a 6 28 pl22a 6 29 vcc - 29 vcc - 30 gnd - 30 gnd - 31 vccio6 6 31 vccio6 6 32 tck - 32 tck - 33 tdi - 33 tdi - 34 tdo - 34 tdo - 35 vccj - 35 vccj - 36 tms - 36 tms - 37 pb2a 5 vref2_5 t 37 pb2a 5 vref2_5 t 38 pb2b 5 vref1_5 c 38 pb2b 5 vref1_5 c 39 vccaux - 39 vccaux - 40 pb4a 5 t 40 pb6a 5 bdqs6 t 41 pb4b 5 c 41 pb6b 5 c 42 vccio5 5 42 vccio5 5 43 pb6a 5 bdqs6 t 43 pb12a 5 t 44 pb6b 5 c 44 pb12b 5 c
4-18 pinout information lattice semiconductor latticeecp2/m family data sheet 45 nc 5 45 pb16a 5 t 46 nc 5 46 pb16b 5 c 47 gnd - 47 gnd - 48 vcc 48 vcc - 49 pb8a 5 pclkt5_0 t 49 pb26a 5 pclkt5_0 t 50 pb8b 5 pclkc5_0 c 50 pb26b 5 pclkc5_0 c 51 gnd - 51 gnd - 52 pb13a 4 pclkt4_0 t 52 pb31a 4 pclkt4_0 t 53 pb13b 4 pclkc4_0 c 53 pb31b 4 pclkc4_0 c 54 vcc - 54 vcc - 55 pb14a 4 t 55 pb34a 4 t 56 pb14b 4 c 56 pb34b 4 c 57 pb16a 4 t 57 pb40a 4 t 58 pb16b 4 c 58 pb40b 4 c 59 pb18a 4 t 59 pb44a 4 t 60 pb18b 4 c 60 pb44b 4 c 61 gnd - 61 gnd - 62 pb20a 4 t 62 pb48a 4 t 63 pb20b 4 c 63 pb48b 4 c 64 vccio4 4 64 vccio4 4 65 pb22a 4 t 65 pb50a 4 t 66 pb22b 4 c 66 pb50b 4 c 67 pb24a 4 bdqs24 t 67 pb52a 4 t 68 pb24b 4 c 68 pb52b 4 c 69 pb26a 4 t 69 pb54a 4 t 70 pb26b 4 c 70 pb54b 4 c 71 pb28a 4 vref2_4 t 71 pb55a 4 vref2_4 t 72 pb28b 4 vref1_4 c 72 pb55b 4 vref1_4 c 73 cfg1 8 73 cfg1 8 74 cfg2 8 74 cfg2 8 75 programn 8 75 programn 8 76 initn 8 76 initn 8 77 cfg0 8 77 cfg0 8 78 cclk 8 78 cclk 8 79 done 8 79 done 8 80 pr29a 8 d0 80 pr29a 8 d0 81 gnd - 81 gnd - 82 pr26a 8 d6 82 pr26a 8 d6 83 vcc - 83 vcc - 84 pr25b 8 d7 c 84 pr25b 8 d7 c 85 vccio8 8 85 vccio8 8 86 pr25a 8 di/csspi0n t 86 pr25a 8 di/csspi0n t 87 pr24b 8 dout/cson c 87 pr24b 8 dout/cson c 88 pr24a 8 busy/sispi t 88 pr24a 8 busy/sispi t lfe2-6e/6se and lfe2-12e/12se logic signal connections: 144 tqfp (cont.) lfe2-6e/6-se lfe2-12e/12se pin number pin function bank dual function differential pin number pin function bank dual function differential
4-19 pinout information lattice semiconductor latticeecp2/m family data sheet 89 vccio3 3 89 vccio3 3 90 vccaux - 90 vccaux - 91 pr20b 3 rlm0_gpllc_in_a** c (lvds)* 91 pr20b 3 rlm0_gpllc_in_a** c (lvds)* 92 pr20a 3 rlm0_gpllt_in_a** t (lvds)* 92 pr20a 3 rlm0_gpllt_in_a** t (lvds)* 93 rlm0_pllcap 3 93 rlm0_pllcap 3 94 vcc - 94 vcc - 95 gnd - 95 gnd - 96 pr17b 3 rlm0_gdllc_in_a** c (lvds)* 96 pr17b 3 rlm0_gdllc_in_a** c (lvds)* 97 pr17a 3 rlm0_gdllt_in_a** t (lvds)* 97 pr17a 3 rlm0_gdllt_in_a** t (lvds)* 98 pr16b 3 vref2_3 c 98 pr16b 3 vref2_3 c 99 pr16a 3 vref1_3 t 99 pr16a 3 vref1_3 t 100 pr15b 3 pclkc3_0 c (lvds)* 100 pr15b 3 pclkc3_0 c (lvds)* 101 pr15a 3 pclkt3_0 t (lvds)* 101 pr15a 3 pclkt3_0 t (lvds)* 102 vcc - 102 vcc - 103 pr13b 2 pclkc2_0 c 103 pr13b 2 pclkc2_0 c 104 pr13a 2 pclkt2_0 t 104 pr13a 2 pclkt2_0 t 105 gnd - 105 gnd - 106 vccio2 2 106 vccio2 2 107 pr2b 2 vref2_2 c (lvds)* 107 pr2b 2 vref2_2 c (lvds)* 108 pr2a 2 vref1_2 t (lvds)* 108 pr2a 2 vref1_2 t (lvds)* 109 pt28b 1 vref2_1 c 109 pt55b 1 vref2_1 c 110 pt28a 1 vref1_1 t 110 pt55a 1 vref1_1 t 111 pt26b 1 c 111 pt54b 1 c 112 pt26a 1 t 112 pt54a 1 t 113 pt24b 1 c 113 pt52b 1 c 114 pt24a 1 t 114 pt52a 1 t 115 pt22b 1 c 115 pt50b 1 c 116 pt22a 1 t 116 pt50a 1 t 117 vccio1 1 117 vccio1 1 118 pt20b 1 c 118 pt48b 1 c 119 pt20a 1 t 119 pt48a 1 t 120 gnd - 120 gnd - 121 pt18b 1 c 121 pt44b 1 c 122 pt18a 1 t 122 pt44a 1 t 123 pt16a 1 123 pt40b 1 c 124 nc 1 124 pt40a 1 t 125 pt14b 1 c 125 pt34b 1 c 126 pt14a 1 t 126 pt34a 1 t 127 nc 1 127 nc 1 128 vcc - 128 vcc - 129 pt12b 1 pclkc1_0 c 129 pt30b 1 pclkc1_0 c 130 pt12a 1 pclkt1_0 t 130 pt30a 1 pclkt1_0 t 131 pt10b 0 pclkc0_0 c 131 pt28b 0 pclkc0_0 c 132 xres 0 132 xres 0 lfe2-6e/6se and lfe2-12e/12se logic signal connections: 144 tqfp (cont.) lfe2-6e/6-se lfe2-12e/12se pin number pin function bank dual function differential pin number pin function bank dual function differential
4-20 pinout information lattice semiconductor latticeecp2/m family data sheet 133 gnd - 133 gnd - 134 pt10a 0 pclkt0_0 t 134 pt28a 0 pclkt0_0 t 135 vcc - 135 vcc - 136 pt6b 0 c 136 pt16b 0 c 137 pt6a 0 t 137 pt16a 0 t 138 gnd - 138 gnd - 139 vccio0 0 139 vccio0 0 140 pt4b 0 c 140 pt6b 0 c 141 pt4a 0 t 141 pt6a 0 t 142 vccaux - 142 vccaux - 143 pt2b 0 vref2_0 c 143 pt2b 0 vref2_0 c 144 pt2a 0 vref1_0 t 144 pt2a 0 vref1_0 t * supports true lvds. other differential signals must be emulated with external resistors. ** these dedicated input pins can be used for gplls or gdlls within the respective quadrant. lfe2-6e/6se and lfe2-12e/12se logic signal connections: 144 tqfp (cont.) lfe2-6e/6-se lfe2-12e/12se pin number pin function bank dual function differential pin number pin function bank dual function differential
4-21 pinout information lattice semiconductor latticeecp2/m family data sheet lfe2-12e/12se and lfe2-20e/20se logic signal connections: 208 pqfp lfe2-12e/12se lfe2-20e/20se pin number pin function bank dual function differential pin number pin function bank dual function differential 1 pl2a 7 vref2_7 t (lvds)* 1 pl2a 7 vref2_7 t (lvds)* 2 pl2b 7 vref1_7 c (lvds)* 2 pl2b 7 vref1_7 c (lvds)* 3 pl4a 7 t (lvds)* 3 pl6a 7 t (lvds)* 4 pl4b 7 c (lvds)* 4 pl6b 7 c (lvds)* 5 gnd - 5 gnd - 6 pl6a 7 t (lvds)* 6 pl12a 7 t (lvds)* 7 vccaux - 7 vccaux - 8 pl6b 7 c (lvds)* 8 pl12b 7 c (lvds)* 9 pl8a 7 t (lvds)* 9 pl14a 7 t (lvds)* 10 vccio7 7 10 vccio7 7 11 pl8b 7 c (lvds)* 11 pl14b 7 c (lvds)* 12 vcc - 12 vcc - 13 gnd - 13 gnd - 14 vccio7 7 14 vccio7 7 15 pl12a 7 t (lvds)* 15 pl18a 7 t (lvds)* 16 pl12b 7 c (lvds)* 16 pl18b 7 c (lvds)* 17 gnd - 17 gnd - 18 pl13a 7 pclkt7_0 t 18 pl19a 7 pclkt7_0 t 19 vcc - 19 vcc - 20 pl13b 7 pclkc7_0 c 20 pl19b 7 pclkc7_0 c 21 pl15a 6 pclkt6_0 t (lvds)* 21 pl21a 6 pclkt6_0 t (lvds)* 22 pl15b 6 pclkc6_0 c (lvds)* 22 pl21b 6 pclkc6_0 c (lvds)* 23 pl16a 6 vref2_6 t 23 pl22a 6 vref2_6 t 24 pl16b 6 vref1_6 c 24 pl22b 6 vref1_6 c 25 gnd - 25 gnd - 26 pl17a 6 llm0_gdllt_in_a** t (lvds)* 26 pl27a 6 llm0_gdllt_in_a** t (lvds)* 27 pl17b 6 llm0_gdllc_in_a** c (lvds)* 27 pl27b 6 llm0_gdllc_in_a** c (lvds)* 28 vcc - 28 vcc - 29 llm0_pllcap 6 29 llm0_pllcap 6 30 vccaux - 30 vccaux - 31 pl20a 6 llm0_gpllt_in_a** t (lvds)* 31 pl30a 6 llm0_gpllt_in_a** t (lvds)* 32 gnd - 32 gnd - 33 pl21a 6 llm0_gpllt_fb_a t 33 pl31a 6 llm0_gpllt_fb_a t 34 pl20b 6 llm0_gpllc_in_a** c (lvds)* 34 pl30b 6 llm0_gpllc_in_a** c (lvds)* 35 pl21b 6 llm0_gpllc_fb_a c 35 pl31b 6 llm0_gpllc_fb_a c 36 pl23a 6 36 pl33a 6 37 pl24a 6 t (lvds)* 37 pl38a 6 t (lvds)* 38 vccio6 6 38 vccio6 6 39 pl24b 6 c (lvds)* 39 pl38b 6 c (lvds)* 40 vcc - 40 vcc - 41 pl26a 6 t (lvds)* 41 pl40a 6 t (lvds)* 42 gnd - 42 gnd - 43 pl26b 6 c (lvds)* 43 pl40b 6 c (lvds)* 44 vccio6 6 44 vccio6 6
4-22 pinout information lattice semiconductor latticeecp2/m family data sheet 45 pl28a 6 ldqs28 t (lvds)* 45 pl42a 6 ldqs42 t (lvds)* 46 pl28b 6 c (lvds)* 46 pl42b 6 c (lvds)* 47 pl30a 6 47 pl44a 6 48 tck - 48 tck - 49 tdi - 49 tdi - 50 tdo - 50 tdo - 51 vccj - 51 vccj - 52 tms - 52 tms - 53 pb2a 5 vref2_5 t 53 pb2a 5 vref2_5 t 54 pb2b 5 vref1_5 c 54 pb2b 5 vref1_5 c 55 vccio5 5 55 vccio5 5 56 pb6a 5 bdqs6 t 56 pb6a 5 bdqs6 t 57 pb6b 5 c 57 pb6b 5 c 58 pb8a 5 t 58 pb8a 5 t 59 pb8b 5 c 59 pb8b 5 c 60 gnd - 60 gnd - 61 pb12a 5 t 61 pb12a 5 t 62 pb12b 5 c 62 pb12b 5 c 63 vccio5 5 63 vccio5 5 64 pb16a 5 t 64 pb16a 5 t 65 pb16b 5 c 65 pb16b 5 c 66 pb18a 5 t 66 pb18a 5 t 67 pb18b 5 c 67 pb18b 5 c 68 gnd - 68 gnd - 69 pb20a 5 t 69 pb30a 5 t 70 vccaux - 70 vccaux - 71 pb20b 5 c 71 pb30b 5 c 72 pb22a 5 t 72 pb32a 5 t 73 pb22b 5 c 73 pb32b 5 c 74 vcc - 74 vcc - 75 pb26a 5 pclkt5_0 t 75 pb35a 5 pclkt5_0 t 76 pb26b 5 pclkc5_0 c 76 pb35b 5 pclkc5_0 c 77 gnd - 77 gnd - 78 pb31a 4 pclkt4_0 t 78 pb40a 4 pclkt4_0 t 79 pb31b 4 pclkc4_0 c 79 pb40b 4 pclkc4_0 c 80 vcc - 80 vcc - 81 gnd - 81 gnd - 82 pb34a 4 t 82 pb42a 4 bdqs42 t 83 pb34b 4 c 83 pb42b 4 c 84 pb36a 4 t 84 pb44a 4 t 85 pb36b 4 c 85 pb44b 4 c 86 vccaux - 86 vccaux - 87 pb40a 4 t 87 pb50a 4 t 88 pb40b 4 c 88 pb50b 4 c lfe2-12e/12se and lfe2-20e/20se logic signal connections: 208 pqfp (cont.) lfe2-12e/12se lfe2-20e/20se pin number pin function bank dual function differential pin number pin function bank dual function differential
4-23 pinout information lattice semiconductor latticeecp2/m family data sheet 89 gnd - 89 gnd - 90 pb42a 4 bdqs42 t 90 pb52a 4 t 91 pb42b 4 c 91 pb52b 4 c 92 pb44a 4 t 92 pb54a 4 t 93 vccio4 4 93 vccio4 4 94 pb44b 4 c 94 pb54b 4 c 95 pb48a 4 t 95 pb58a 4 t 96 pb48b 4 c 96 pb58b 4 c 97 vcc - 97 vcc - 98 pb52a 4 t 98 pb60a 4 bdqs60 t 99 pb52b 4 c 99 pb60b 4 c 100 vccio4 4 100 vccio4 4 101 pb54a 4 101 pb63a 4 102 gnd - 102 gnd - 103 pb55a 4 vref2_4 t 103 pb64a 4 vref2_4 t 104 pb55b 4 vref1_4 c 104 pb64b 4 vref1_4 c 105 cfg1 8 105 cfg1 8 106 programn 8 106 programn 8 107 cfg2 8 107 cfg2 8 108 initn 8 108 initn 8 109 cfg0 8 109 cfg0 8 110 cclk 8 110 cclk 8 111 done 8 111 done 8 112 pr29a 8 d0 112 pr43a 8 d0 113 vccio8 8 113 vccio8 8 114 pr26a 8 d6 114 pr40a 8 d6 115 gnd - 115 gnd - 116 vcc - 116 vcc - 117 pr25b 8 d7 c 117 pr39b 8 d7 c 118 vccio8 8 118 vccio8 8 119 pr25a 8 di/csspi0n t 119 pr39a 8 di/csspi0n t 120 pr24b 8 dout/cson c 120 pr38b 8 dout/cson c 121 pr24a 8 busy/sispi t 121 pr38a 8 busy/sispi t 122 gnd - 122 gnd - 123 vccio3 3 123 vccio3 3 124 pr21a 3 rlm0_gpllt_fb_a 124 pr31a 3 rlm0_gpllt_fb_a 125 vccaux - 125 vccaux - 126 pr20b 3 rlm0_gpllc_in_a** c (lvds)* 126 pr30b 3 rlm0_gpllc_in_a** c (lvds)* 127 pr20a 3 rlm0_gpllt_in_a** t (lvds)* 127 pr30a 3 rlm0_gpllt_in_a** t (lvds)* 128 rlm0_pllcap 3 128 rlm0_pllcap 3 129 vcc - 129 vcc - 130 pr18b 3 rlm0_gdllc_fb_a c 130 pr28b 3 rlm0_gdllc_fb_a c 131 pr18a 3 rlm0_gdllt_fb_a t 131 pr28a 3 rlm0_gdllt_fb_a** t 132 pr17b 3 rlm0_gdllc_in_a** c (lvds)* 132 pr27b 3 rlm0_gdllc_in_a c (lvds)* lfe2-12e/12se and lfe2-20e/20se logic signal connections: 208 pqfp (cont.) lfe2-12e/12se lfe2-20e/20se pin number pin function bank dual function differential pin number pin function bank dual function differential
4-24 pinout information lattice semiconductor latticeecp2/m family data sheet 133 pr17a 3 rlm0_gdllt_in_a** t (lvds)* 133 pr27a 3 rlm0_gdllt_in_a** t (lvds)* 134 pr16b 3 vref2_3 c 134 pr22b 3 vref2_3 c 135 vccio3 3 135 vccio3 3 136 pr16a 3 vref1_3 t 136 pr22a 3 vref1_3 t 137 pr15b 3 pclkc3_0 c (lvds)* 137 pr21b 3 pclkc3_0 c (lvds)* 138 pr15a 3 pclkt3_0 t (lvds)* 138 pr21a 3 pclkt3_0 t (lvds)* 139 gnd - 139 gnd - 140 vcc - 140 vcc - 141 pr13b 2 pclkc2_0 c 141 pr19b 2 pclkc2_0 c 142 pr13a 2 pclkt2_0 t 142 pr19a 2 pclkt2_0 t 143 vccio2 2 143 vccio2 2 144 pr12a 2 144 pr16a 2 rdqs16 145 gnd - 145 gnd - 146 vcc - 146 vcc - 147 pr8b 2 c (lvds)* 147 pr14b 2 c (lvds)* 148 vccio2 2 148 vccio2 2 149 pr8a 2 t (lvds)* 149 pr14a 2 t (lvds)* 150 pr6b 2 c (lvds)* 150 pr12b 2 c (lvds)* 151 vccaux - 151 vccaux - 152 pr6a 2 t (lvds)* 152 pr12a 2 t (lvds)* 153 pr4b 2 c (lvds)* 153 pr6b 2 c (lvds)* 154 pr4a 2 t (lvds)* 154 pr6a 2 t (lvds)* 155 pr2b 2 vref2_2 c (lvds)* 155 pr2b 2 vref2_2 c (lvds)* 156 pr2a 2 vref1_2 t (lvds)* 156 pr2a 2 vref1_2 t (lvds)* 157 pt55b 1 vref2_1 c 157 pt64b 1 vref2_1 c 158 pt55a 1 vref1_1 t 158 pt64a 1 vref1_1 t 159 gnd - 159 gnd - 160 pt54b 1 c 160 pt62b 1 c 161 pt54a 1 t 161 pt62a 1 t 162 vccio1 1 162 vccio1 1 163 pt52b 1 c 163 pt60b 1 c 164 pt52a 1 t 164 pt60a 1 t 165 pt50b 1 c 165 pt58b 1 c 166 pt50a 1 t 166 pt58a 1 t 167 pt48b 1 c 167 pt56b 1 c 168 pt48a 1 t 168 pt56a 1 t 169 gnd - 169 gnd - 170 vccio1 1 170 vccio1 1 171 vcc - 171 vcc - 172 pt40b 1 c 172 pt50b 1 c 173 pt40a 1 t 173 pt50a 1 t 174 vccaux - 174 vccaux - 175 gnd - 175 gnd - 176 pt36b 1 c 176 pt44b 1 c lfe2-12e/12se and lfe2-20e/20se logic signal connections: 208 pqfp (cont.) lfe2-12e/12se lfe2-20e/20se pin number pin function bank dual function differential pin number pin function bank dual function differential
4-25 pinout information lattice semiconductor latticeecp2/m family data sheet 177 pt36a 1 t 177 pt44a 1 t 178 pt34b 1 c 178 pt42b 1 c 179 pt34a 1 t 179 pt42a 1 t 180 pt30b 1 pclkc1_0 c 180 pt39b 1 pclkc1_0 c 181 pt30a 1 pclkt1_0 t 181 pt39a 1 pclkt1_0 t 182 xres 1 182 xres 1 183 pt28b 0 pclkc0_0 c 183 pt37b 0 pclkc0_0 c 184 gnd - 184 gnd - 185 pt28a 0 pclkt0_0 t 185 pt37a 0 pclkt0_0 t 186 pt26b 0 c 186 pt36b 0 c 187 pt26a 0 t 187 pt36a 0 t 188 vcc - 188 vcc - 189 pt20b 0 c 189 pt30b 0 c 190 vccaux - 190 vccaux - 191 pt20a 0 t 191 pt30a 0 t 192 gnd - 192 gnd - 193 pt18b 0 c 193 pt26b 0 c 194 pt18a 0 t 194 pt26a 0 t 195 vccio0 0 195 vccio0 0 196 pt16b 0 c 196 pt20b 0 c 197 pt16a 0 t 197 pt20a 0 t 198 vcc - 198 vcc - 199 pt12b 0 c 199 pt12b 0 c 200 pt12a 0 t 200 pt12a 0 t 201 gnd - 201 gnd - 202 pt8b 0 c 202 pt8b 0 c 203 pt8a 0 t 203 pt8a 0 t 204 pt6b 0 c 204 pt6b 0 c 205 pt6a 0 t 205 pt6a 0 t 206 vccio0 0 206 vccio0 0 207 pt2b 0 vref2_0 c 207 pt2b 0 vref2_0 c 208 pt2a 0 vref1_0 t 208 pt2a 0 vref1_0 t * supports true lvds. other differential signals must be emulated with external resistors. ** these dedicated input pins can be used for gplls or gdlls within the respective quadrant. lfe2-12e/12se and lfe2-20e/20se logic signal connections: 208 pqfp (cont.) lfe2-12e/12se lfe2-20e/20se pin number pin function bank dual function differential pin number pin function bank dual function differential
4-26 pinout information lattice semiconductor latticeecp2/m family data sheet lfe2-6e/6se and lfe2-12e/12se logic signal connections: 256 fpbga lfe2-6e/6se lfe2-12e/12se ball number ball function bank dual function differential ball number ball function bank dual function differential c3 pl2a 7 vref2_7 t (lvds)* c3 pl2a 7 vref2_7 t (lvds)* c2 pl2b 7 vref1_7 c (lvds)* c2 pl2b 7 vref1_7 c (lvds)* vccio vccio7 7 vccio vccio7 7 --- --- d3 pl5a 7 t d3 pl5a 7 t d4 pl4a 7 t (lvds)* d4 pl4a 7 t (lvds)* d2 pl5b 7 c d2 pl5b 7 c gnd gndio7 7 gndio gndio7 7 e4 pl4b 7 c (lvds)* e4 pl4b 7 c (lvds)* b1 pl7a 7 t b1 pl7a 7 t c1 pl7b 7 c c1 pl7b 7 c f5 pl9a 7 t f5 pl9a 7 t vccio vccio7 7 vccio vccio7 7 f4 pl8a 7 t (lvds)* f4 pl8a 7 t (lvds)* g6 pl9b 7 c g6 pl9b 7 c g4 pl8b 7 c (lvds)* g4 pl8b 7 c (lvds)* d1 pl10a 7 ldqs10 t (lvds)* d1 pl10a 7 ldqs10 t (lvds)* gnd gndio7 7 gnd gndio7 7 e1 pl10b 7 c (lvds)* e1 pl10b 7 c (lvds)* f3 pl11a 7 t f3 pl11a 7 t g3 pl11b 7 c g3 pl11b 7 c vccio vccio7 7 vccio vccio7 7 f2 pl12a 7 t (lvds)* f2 pl12a 7 t (lvds)* f1 pl12b 7 c (lvds)* f1 pl12b 7 c (lvds)* gnd gndio7 7 gnd gndio7 7 g2 pl13a 7 pclkt7_0 t g2 pl13a 7 pclkt7_0 t g1 pl13b 7 pclkc7_0 c g1 pl13b 7 pclkc7_0 c h6 pl15a 6 pclkt6_0 t (lvds)* h6 pl15a 6 pclkt6_0 t (lvds)* vccio vccio6 6 vccio vccio6 6 h5 pl15b 6 pclkc6_0 c (lvds)* h5 pl15b 6 pclkc6_0 c (lvds)* h4 pl16a 6 vref2_6 t h4 pl16a 6 vref2_6 t gnd gndio6 6 gnd gndio6 6 h3 pl16b 6 vref1_6 c h3 pl16b 6 vref1_6 c h2 pl17a 6 llm0_gdllt_in_a** t (lvds)* h2 pl17a 6 llm0_gdllt_in_a** t (lvds)* h1 pl17b 6 llm0_gdllc_in_a** c (lvds)* h1 pl17b 6 llm0_gdllc_in_a** c (lvds)* g10 vcc - g10 vcc - j4 pl18a 6 llm0_gdllt_fb_a t j4 pl18a 6 llm0_gdllt_fb_a t j5 pl18b 6 llm0_gdllc_fb_a c j5 pl18b 6 llm0_gdllc_fb_a c j6 llm0_pllcap 6 j6 llm0_pllcap 6 k4 pl20a 6 llm0_gpllt_in_a** t (lvds)* k4 pl20a 6 llm0_gpllt_in_a** t (lvds)* gnd gndio6 6 gnd gndio6 6 j1 pl21a 6 llm0_gpllt_fb_a t j1 pl21a 6 llm0_gpllt_fb_a t k3 pl20b 6 llm0_gpllc_in_a** c (lvds)* k3 pl20b 6 llm0_gpllc_in_a** c (lvds)* vccio vccio6 6 vccio vccio6 6
4-27 pinout information lattice semiconductor latticeecp2/m family data sheet j2 pl21b 6 llm0_gpllc_fb_a c j2 pl21b 6 llm0_gpllc_fb_a c gnd gndio6 6 gnd gndio6 6 l2 pl24a 6 t (lvds)* l2 pl24a 6 t (lvds)* k2 pl25a 6 t k2 pl25a 6 t l3 pl24b 6 c (lvds)* l3 pl24b 6 c (lvds)* k1 pl25b 6 c k1 pl25b 6 c vccio vccio6 6 vccio vccio6 6 l4 pl26a 6 t (lvds)* l4 pl26a 6 t (lvds)* l1 pl27a 6 t l1 pl27a 6 t l5 pl26b 6 c (lvds)* l5 pl26b 6 c (lvds)* m1 pl27b 6 c m1 pl27b 6 c gnd gndio6 6 gnd gndio6 6 n1 pl29a 6 t n1 pl29a 6 t n2 pl28a 6 ldqs28 t (lvds)* n2 pl28a 6 ldqs28 t (lvds)* p1 pl29b 6 c p1 pl29b 6 c vccio vccio6 6 vccio vccio6 6 p2 pl28b 6 c (lvds)* p2 pl28b 6 c (lvds)* r1 pl30a 6 t (lvds)* r1 pl30a 6 t (lvds)* gnd gndio6 6 gnd gndio6 6 r2 pl30b 6 c (lvds)* r2 pl30b 6 c (lvds)* n4 tdi - n4 tdi - m4 tck - m4 tck - p3 tdo - p3 tdo - n3 tms - n3 tms - k7 vccj - k7 vccj - m5 pb2a 5 vref2_5 t m5 pb2a 5 vref2_5 t k6 nc - k6 pb3a 5 m6 pb2b 5 vref1_5 c m6 pb2b 5 vref1_5 c r3 nc - r3 pb5a 5 t p4 nc - p4 pb5b 5 c - - - vcc vccio 5 - - - gnd gndio5 5 n5 pb3a 5 t n5 pb21a 5 t n6 pb3b 5 c n6 pb21b 5 c t2 pb4a 5 t t2 pb22a 5 t p6 pb5a 5 t p6 pb23a 5 t vccio vccio5 5 vccio vccio5 5 t3 pb4b 5 c t3 pb22b 5 c r6 pb5b 5 c r6 pb23b 5 c gnd gndio5 5 gnd gndio5 5 r4 pb6a 5 bdqs6 t r4 pb24a 5 bdqs24 t l6 pb7a 5 t l6 pb25a 5 t t4 pb6b 5 c t4 pb24b 5 c l7 pb7b 5 c l7 pb25b 5 c lfe2-6e/6se and lfe2-12e/12se logic signal connections: 256 fpbga (cont.) lfe2-6e/6se lfe2-12e/12se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-28 pinout information lattice semiconductor latticeecp2/m family data sheet n7 pb8a 5 pclkt5_0 t n7 pb26a 5 pclkt5_0 t vccio vccio5 5 vccio vccio5 5 m8 pb8b 5 pclkc5_0 c m8 pb26b 5 pclkc5_0 c gnd gndio5 5 gnd gndio5 5 p7 pb13a 4 pclkt4_0 t p7 pb31a 4 pclkt4_0 t r8 pb13b 4 pclkc4_0 c r8 pb31b 4 pclkc4_0 c vccio vccio4 4 vccio vccio4 4 t5 pb14a 4 t t5 pb32a 4 t t6 pb14b 4 c t6 pb32b 4 c t8 pb15a 4 bdqs15 t t8 pb33a 4 bdqs33 t gnd gndio4 4 gnd gndio4 4 r7 pb16a 4 t r7 pb34a 4 t t9 pb15b 4 c t9 pb33b 4 c t7 pb16b 4 c t7 pb34b 4 c l8 pb17a 4 t l8 pb35a 4 t vccio vccio4 4 vccio vccio4 4 p8 pb18a 4 t p8 pb36a 4 t l9 pb17b 4 c l9 pb35b 4 c n8 pb18b 4 c n8 pb36b 4 c r9 pb19a 4 t r9 pb37a 4 t gnd gndio4 4 gnd gndio4 4 r10 pb19b 4 c r10 pb37b 4 c - - - vcc vccio 4 - - - gnd gndio4 4 n9 pb20a 4 t n9 pb47a 4 t t10 pb21a 4 t t10 pb48a 4 t m9 pb20b 4 c m9 pb47b 4 c r11 pb21b 4 c r11 pb48b 4 c p10 pb22a 4 t p10 pb49a 4 t n11 pb23a 4 t n11 pb50a 4 t vccio vccio4 4 vccio vccio4 4 n10 pb22b 4 c n10 pb49b 4 c p11 pb23b 4 c p11 pb50b 4 c t11 pb24a 4 bdqs24 t t11 pb51a 4 bdqs51 t gnd gndio4 4 gnd gndio4 4 m11 pb25a 4 t m11 pb52a 4 t t12 pb24b 4 c t12 pb51b 4 c l11 pb25b 4 c l11 pb52b 4 c t13 pb26a 4 t t13 pb53a 4 t r13 pb27a 4 t r13 pb54a 4 t vccio vccio4 4 vccio vccio4 4 t14 pb26b 4 c t14 pb53b 4 c p13 pb27b 4 c p13 pb54b 4 c gnd gndio4 4 gnd gndio4 4 lfe2-6e/6se and lfe2-12e/12se logic signal connections: 256 fpbga (cont.) lfe2-6e/6se lfe2-12e/12se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-29 pinout information lattice semiconductor latticeecp2/m family data sheet n12 pb28a 4 vref2_4 t n12 pb55a 4 vref2_4 t m12 pb28b 4 vref1_4 c m12 pb55b 4 vref1_4 c r15 cfg2 8 r15 cfg2 8 n14 cfg1 8 n14 cfg1 8 n13 programn 8 n13 programn 8 n15 cfg0 8 n15 cfg0 8 p15 pr30b 8 w riten c p15 pr30b 8 w riten c l12 initn 8 l12 initn 8 n16 pr29b 8 csn c n16 pr29b 8 csn c gnd gndio8 8 gnd gndio8 8 r14 cclk 8 r14 cclk 8 p14 pr30a 8 cs1n t p14 pr30a 8 cs1n t m13 done 8 m13 done 8 r16 pr28b 8 d1 c r16 pr28b 8 d1 c vccio vccio8 8 vccio vccio8 8 m16 pr29a 8 d0 t m16 pr29a 8 d0 t p16 pr28a 8 d2 t p16 pr28a 8 d2 t l15 pr27b 8 d3 c l15 pr27b 8 d3 c gnd gndio8 8 gnd gndio8 8 l14 pr26a 8 d6 t l14 pr26a 8 d6 t l16 pr27a 8 d4 t l16 pr27a 8 d4 t l10 pr25b 8 d7 c l10 pr25b 8 d7 c l13 pr26b 8 d5 c l13 pr26b 8 d5 c vccio vccio8 8 vccio vccio8 8 k11 pr25a 8 di/csspi0n t k11 pr25a 8 di/csspi0n t k14 pr24b 8 dout/cson c k14 pr24b 8 dout/cson c k13 pr24a 8 busy/sispi t k13 pr24a 8 busy/sispi t gnd gndio8 8 gnd gndio8 8 k15 pr21b 3 rlm0_gpllc_fb_a c k15 pr21b 3 rlm0_gpllc_fb_a c vccio vccio3 3 vccio vccio3 3 k16 pr21a 3 rlm0_gpllt_fb_a t k16 pr21a 3 rlm0_gpllt_fb_a t gnd gndio3 3 gnd gndio3 3 j16 pr20b 3 rlm0_gpllc_in_a** c (lvds)* j16 pr20b 3 rlm0_gpllc_in_a** c (lvds)* j15 pr20a 3 rlm0_gpllt_in_a** t (lvds)* j15 pr20a 3 rlm0_gpllt_in_a** t (lvds)* j14 rlm0_pllcap 3 j14 rlm0_pllcap 3 j13 pr18b 3 rlm0_gdllc_fb_a c j13 pr18b 3 rlm0_gdllc_fb_a c j12 pr18a 3 rlm0_gdllt_fb_a t j12 pr18a 3 rlm0_gdllt_fb_a t h12 pr17b 3 rlm0_gdllc_in_a** c (lvds)* h12 pr17b 3 rlm0_gdllc_in_a** c (lvds)* gnd gndio3 3 gnd gndio3 3 h13 pr17a 3 rlm0_gdllt_in_a** t (lvds)* h13 pr17a 3 rlm0_gdllt_in_a** t (lvds)* h15 pr16b 3 vref2_3 c h15 pr16b 3 vref2_3 c vccio vccio3 3 vccio vccio3 3 h16 pr16a 3 vref1_3 t h16 pr16a 3 vref1_3 t h11 pr15b 3 pclkc3_0 c (lvds)* h11 pr15b 3 pclkc3_0 c (lvds)* lfe2-6e/6se and lfe2-12e/12se logic signal connections: 256 fpbga (cont.) lfe2-6e/6se lfe2-12e/12se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-30 pinout information lattice semiconductor latticeecp2/m family data sheet j11 pr15a 3 pclkt3_0 t (lvds)* j11 pr15a 3 pclkt3_0 t (lvds)* g16 pr13b 2 pclkc2_0 c g16 pr13b 2 pclkc2_0 c gnd gndio2 2 gnd gndio2 2 g15 pr13a 2 pclkt2_0 t g15 pr13a 2 pclkt2_0 t f15 pr11b 2 c f15 pr11b 2 c g11 pr12b 2 c (lvds)* g11 pr12b 2 c (lvds)* f14 pr11a 2 t f14 pr11a 2 t vccio vccio2 2 vccio vccio2 2 f12 pr12a 2 t (lvds)* f12 pr12a 2 t (lvds)* g14 pr10b 2 c (lvds)* g14 pr10b 2 c (lvds)* g13 pr10a 2 rdqs10 t (lvds)* g13 pr10a 2 rdqs10 t (lvds)* gnd gndio2 2 gnd gndio2 2 f16 pr8b 2 c (lvds)* f16 pr8b 2 c (lvds)* f9 pr9b 2 c f9 pr9b 2 c e16 pr8a 2 t (lvds)* e16 pr8a 2 t (lvds)* f10 pr9a 2 t f10 pr9a 2 t vccio vccio2 2 vccio vccio2 2 d16 pr7b 2 c d16 pr7b 2 c d15 pr7a 2 t d15 pr7a 2 t c15 pr4b 2 c (lvds)* c15 pr4b 2 c (lvds)* c16 pr5b 2 c c16 pr5b 2 c gnd gndio2 2 gnd gndio2 2 d14 pr4a 2 t (lvds)* d14 pr4a 2 t (lvds)* b16 pr5a 2 t b16 pr5a 2 t f13 pr2b 2 vref2_2 c (lvds)* f13 pr2b 2 vref2_2 c (lvds)* vccio vccio2 2 vccio vccio2 2 e13 pr2a 2 vref1_2 t (lvds)* e13 pr2a 2 vref1_2 t (lvds)* f11 pt28b 1 vref2_1 c f11 pt55b 1 vref2_1 c e11 pt28a 1 vref1_1 t e11 pt55a 1 vref1_1 t gnd gndio1 1 gnd gndio1 1 a15 pt27b 1 c a15 pt54b 1 c e12 pt26b 1 c e12 pt53b 1 c b15 pt27a 1 t b15 pt54a 1 t vccio vccio1 1 vccio vccio1 1 d12 pt26a 1 t d12 pt53a 1 t b14 pt25b 1 c b14 pt52b 1 c c14 pt24b 1 c c14 pt51b 1 c a14 pt25a 1 t a14 pt52a 1 t d13 pt24a 1 t d13 pt51a 1 t c13 pt23b 1 c c13 pt50b 1 c gnd gndio1 1 gnd gndio1 1 a13 pt22b 1 c a13 pt49b 1 c b13 pt23a 1 t b13 pt50a 1 t vccio vccio1 1 vccio vccio1 1 lfe2-6e/6se and lfe2-12e/12se logic signal connections: 256 fpbga (cont.) lfe2-6e/6se lfe2-12e/12se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-31 pinout information lattice semiconductor latticeecp2/m family data sheet a12 pt22a 1 t a12 pt49a 1 t b11 pt21b 1 c b11 pt48b 1 c d11 pt20b 1 c d11 pt47b 1 c a11 pt21a 1 t a11 pt48a 1 t c11 pt20a 1 t c11 pt47a 1 t - - - gnd gndio1 1 - - - vcc vccio 1 d10 pt19b 1 c d10 pt37b 1 c c10 pt19a 1 t c10 pt37a 1 t gnd gndio1 1 gnd gndio1 1 b10 pt18b 1 c b10 pt36b 1 c a9 pt17b 1 c a9 pt35b 1 c a10 pt18a 1 t a10 pt36a 1 t b9 pt17a 1 t b9 pt35a 1 t vccio vccio1 1 vccio vccio1 1 a8 pt16b 1 c a8 pt34b 1 c d9 pt15b 1 c d9 pt33b 1 c b8 pt16a 1 t b8 pt34a 1 t c9 pt15a 1 t c9 pt33a 1 t gnd gndio1 1 gnd gndio1 1 b7 pt14b 1 c b7 pt32b 1 c e9 pt13b 1 c e9 pt31b 1 c a7 pt14a 1 t a7 pt32a 1 t d8 pt13a 1 t d8 pt31a 1 t vccio vccio1 1 vccio vccio1 1 a6 pt12b 1 pclkc1_0 c a6 pt30b 1 pclkc1_0 c b6 pt12a 1 pclkt1_0 t b6 pt30a 1 pclkt1_0 t e6 xres - e6 xres 1 f8 pt10b 0 pclkc0_0 c f8 pt28b 0 pclkc0_0 c gnd gndio0 0 gnd gndio0 0 e8 pt10a 0 pclkt0_0 t e8 pt28a 0 pclkt0_0 t a5 pt9b 0 c a5 pt27b 0 c a3 pt8b 0 c a3 pt26b 0 c a4 pt9a 0 t a4 pt27a 0 t vccio vccio0 0 vccio vccio0 0 b3 pt8a 0 t b3 pt26a 0 t a2 pt7b 0 c a2 pt25b 0 c c7 pt6b 0 c c7 pt24b 0 c b2 pt7a 0 t b2 pt25a 0 t d7 pt6a 0 t d7 pt24a 0 t d6 pt5b 0 c d6 pt23b 0 c gnd gndio0 0 gnd gndio0 0 f7 pt4b 0 c f7 pt22b 0 c c6 pt5a 0 t c6 pt23a 0 t lfe2-6e/6se and lfe2-12e/12se logic signal connections: 256 fpbga (cont.) lfe2-6e/6se lfe2-12e/12se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-32 pinout information lattice semiconductor latticeecp2/m family data sheet vccio vccio0 0 vccio vccio0 0 f6 pt4a 0 t f6 pt22a 0 t c4 pt3b 0 c c4 pt21b 0 c b4 pt3a 0 t b4 pt21a 0 t - - - gnd gndio0 0 - - - vcc vccio 0 d5 pt2b 0 vref2_0 c d5 pt2b 0 vref2_0 c e5 pt2a 0 vref1_0 t e5 pt2a 0 vref1_0 t g7 vcc - g7 vcc - g9 vcc - g9 vcc - h7 vcc - h7 vcc - j10 vcc - j10 vcc - k10 vcc - k10 vcc - k8 vcc - k8 vcc - g8 vccaux - g8 vccaux - h10 vccaux - h10 vccaux - j7 vccaux - j7 vccaux - k9 vccaux - k9 vccaux - c5 vccio 0 c5 vccio 0 e7 vccio 0 e7 vccio 0 c12 vccio 1 c12 vccio 1 e10 vccio 1 e10 vccio 1 e14 vccio 2 e14 vccio 2 g12 vccio 2 g12 vccio 2 k12 vccio 3 k12 vccio 3 m14 vccio 3 m14 vccio 3 m10 vccio 4 m10 vccio 4 p12 vccio 4 p12 vccio 4 m7 vccio 5 m7 vccio 5 p5 vccio 5 p5 vccio 5 k5 vccio 6 k5 vccio 6 m3 vccio 6 m3 vccio 6 e3 vccio 7 e3 vccio 7 g5 vccio 7 g5 vccio 7 t15 vccio 8 t15 vccio 8 a1 gnd - a1 gnd - a16 gnd - a16 gnd - b12 gnd - b12 gnd - b5 gnd - b5 gnd - c8 gnd - c8 gnd - e15 gnd - e15 gnd - e2 gnd - e2 gnd - h14 gnd - h14 gnd - h8 gnd - h8 gnd - lfe2-6e/6se and lfe2-12e/12se logic signal connections: 256 fpbga (cont.) lfe2-6e/6se lfe2-12e/12se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-33 pinout information lattice semiconductor latticeecp2/m family data sheet h9 gnd - h9 gnd - j3 gnd - j3 gnd - j8 gnd - j8 gnd - j9 gnd - j9 gnd - m15 gnd - m15 gnd - m2 gnd - m2 gnd - p9 gnd - p9 gnd - r12 gnd - r12 gnd - r5 gnd - r5 gnd - t1 gnd - t1 gnd - t16 gnd - t16 gnd - * supports true lvds. other differential signals must be emulated with external resistors. ** these dedicated input pins can be used for gplls or gdlls within the respective quadrant. lfe2-6e/6se and lfe2-12e/12se logic signal connections: 256 fpbga (cont.) lfe2-6e/6se lfe2-12e/12se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-34 pinout information lattice semiconductor latticeecp2/m family data sheet lfe2-20e/20se logic signal connections: 256 fpbga ball number ball function bank dual function differential c3 pl2a 7 vref2_7 t* c2 pl2b 7 vref1_7 c* vccio vccio7 7 gnd gndio 7 d3 pl7a 7 t d4 pl6a 7 t* d2 pl7b 7 c gnd gndio 7 e4 pl6b 7 c* b1 pl13a 7 t c1 pl13b 7 c f5 pl15a 7 t f4 pl14a 7 t* g6 pl15b 7 c g4 pl14b 7 c* d1 pl16a 7 ldqs16 t* gnd gndio 7 vcc vccio 7 e1 pl16b 7 c* f3 pl17a 7 t g3 pl17b 7 c vccio vccio7 7 f2 pl18a 7 t* f1 pl18b 7 c* gnd gndio 7 g2 pl19a 7 pclkt7_0 t g1 pl19b 7 pclkc7_0 c h6 pl21a 6 pclkt6_0 t* vccio vccio6 6 h5 pl21b 6 pclkc6_0 c* h4 pl22a 6 vref2_6 t gnd gndio 6 h3 pl22b 6 vref1_6 c h2 pl27a 6 llm0_gdllt_in_a** t* h1 pl27b 6 llm0_gdllc_in_a** c* g10 vcc - j4 pl28a 6 llm0_gdllt_fb_a t j5 pl28b 6 llm0_gdllc_fb_a c j6 llm0_pllcap 6 k4 pl30a 6 llm0_gpllt_in_a** t* gnd gndio 6 j1 pl31a 6 llm0_gpllt_fb_a t k3 pl30b 6 llm0_gpllc_in_a** c*
4-35 pinout information lattice semiconductor latticeecp2/m family data sheet vccio vccio6 6 j2 pl31b 6 llm0_gpllc_fb_a c gnd gndio 6 l2 pl38a 6 t* k2 pl39a 6 t l3 pl38b 6 c* k1 pl39b 6 c vccio vccio6 6 l4 pl40a 6 t* l1 pl41a 6 t l5 pl40b 6 c* m1 pl41b 6 c gnd gndio 6 n1 pl43a 6 t n2 pl42a 6 ldqs42 t* p1 pl43b 6 c vccio vccio6 6 p2 pl42b 6 c* r1 pl44a 6 t* gnd gndio 6 r2 pl44b 6 c* n4 tdi - m4 tck - p3 tdo - n3 tms - k7 vccj - m5 pb2a 5 vref2_5 t k6 pb3a 5 m6 pb2b 5 vref1_5 c r3 pb5a 5 t p4 pb5b 5 c vcc vccio 5 gnd gndio 5 n5 pb30a 5 t n6 pb30b 5 c t2 pb31a 5 t p6 pb32a 5 t vccio vccio5 5 t3 pb31b 5 c r6 pb32b 5 c gnd gndio 5 r4 pb33a 5 bdqs33 t l6 pb34a 5 t t4 pb33b 5 c lfe2-20e/20se logic signal connections: 256 fpbga (cont.) ball number ball function bank dual function differential
4-36 pinout information lattice semiconductor latticeecp2/m family data sheet l7 pb34b 5 c n7 pb35a 5 pclkt5_0 t vccio vccio5 5 m8 pb35b 5 pclkc5_0 c gnd gndio 5 p7 pb40a 4 pclkt4_0 t r8 pb40b 4 pclkc4_0 c vccio vccio4 4 t5 pb41a 4 t t6 pb41b 4 c t8 pb42a 4 bdqs42 t gnd gndio 4 r7 pb43a 4 t t9 pb42b 4 c t7 pb43b 4 c l8 pb44a 4 t vccio vccio4 4 p8 pb45a 4 t l9 pb44b 4 c n8 pb45b 4 c r9 pb46a 4 t gnd gndio 4 r10 pb46b 4 c vcc vccio 4 gnd gndio 4 n9 pb56a 4 t t10 pb57a 4 t m9 pb56b 4 c r11 pb57b 4 c p10 pb58a 4 t n11 pb59a 4 t vccio vccio4 4 n10 pb58b 4 c p11 pb59b 4 c t11 pb60a 4 bdqs60 t gnd gndio 4 m11 pb61a 4 t t12 pb60b 4 c l11 pb61b 4 c t13 pb62a 4 t r13 pb63a 4 t vccio vccio4 4 t14 pb62b 4 c p13 pb63b 4 c lfe2-20e/20se logic signal connections: 256 fpbga (cont.) ball number ball function bank dual function differential
4-37 pinout information lattice semiconductor latticeecp2/m family data sheet gnd gndio 4 n12 pb64a 4 vref2_4 t m12 pb64b 4 vref1_4 c r15 cfg2 8 n14 cfg1 8 n13 programn 8 n15 cfg0 8 p15 pr44b 8 w riten c l12 initn 8 n16 pr43b 8 csn c gnd gndio 8 r14 cclk 8 p14 pr44a 8 cs1n t m13 done 8 r16 pr42b 8 d1 c vccio vccio8 8 m16 pr43a 8 d0 t p16 pr42a 8 d2 t l15 pr41b 8 d3 c gnd gndio 8 l14 pr40a 8 d6 t l16 pr41a 8 d4 t l10 pr39b 8 d7 c l13 pr40b 8 d5 c vccio vccio8 8 k11 pr39a 8 di t k14 pr38b 8 dout,cson c k13 pr38a 8 busy t gnd gndio 8 k15 pr31b 3 rlm0_gpllc_fb_a c vccio vccio3 3 k16 pr31a 3 rlm0_gpllt_fb_a t gnd gndio 3 j16 pr30b 3 rlm0_gpllc_in_a** c* j15 pr30a 3 rlm0_gpllt_in_a** t* j14 rlm0_pllcap 3 j13 pr28b 3 rlm0_gdllc_fb_a c j12 pr28a 3 rlm0_gdllt_fb_a t h12 pr27b 3 rlm0_gdllc_in_a** c* gnd gndio 3 h13 pr27a 3 rlm0_gdllt_in_a** t* h15 pr22b 3 vref2_3 c vccio vccio3 3 h16 pr22a 3 vref1_3 t lfe2-20e/20se logic signal connections: 256 fpbga (cont.) ball number ball function bank dual function differential
4-38 pinout information lattice semiconductor latticeecp2/m family data sheet h11 pr21b 3 pclkc3_0 c* j11 pr21a 3 pclkt3_0 t* g16 pr19b 2 pclkc2_0 c gnd gndio 2 g15 pr19a 2 pclkt2_0 t f15 pr17b 2 c g11 pr18b 2 c* f14 pr17a 2 t vccio vccio2 2 f12 pr18a 2 t* g14 pr16b 2 c* g13 pr16a 2 rdqs16 t* gnd gndio 2 f16 pr14b 2 c* f9 pr15b 2 c e16 pr14a 2 t* f10 pr15a 2 t vccio vccio2 2 d16 pr13b 2 c d15 pr13a 2 t c15 pr6b 2 c* c16 pr7b 2 c gnd gndio 2 d14 pr6a 2 t* b16 pr7a 2 t f13 pr2b 2 vref2_2 c* vccio vccio2 2 e13 pr2a 2 vref1_2 t* f11 pt64b 1 vref2_1 c e11 pt64a 1 vref1_1 t gnd gndio 1 a15 pt63b 1 c e12 pt62b 1 c b15 pt63a 1 t vccio vccio1 1 d12 pt62a 1 t b14 pt61b 1 c c14 pt60b 1 c a14 pt61a 1 t d13 pt60a 1 t c13 pt59b 1 c gnd gndio 1 a13 pt58b 1 c b13 pt59a 1 t lfe2-20e/20se logic signal connections: 256 fpbga (cont.) ball number ball function bank dual function differential
4-39 pinout information lattice semiconductor latticeecp2/m family data sheet vccio vccio1 1 a12 pt58a 1 t b11 pt57b 1 c d11 pt56b 1 c a11 pt57a 1 t c11 pt56a 1 t gnd gndio 1 vcc vccio 1 d10 pt46b 1 c c10 pt46a 1 t gnd gndio 1 b10 pt45b 1 c a9 pt44b 1 c a10 pt45a 1 t b9 pt44a 1 t vccio vccio1 1 a8 pt43b 1 c d9 pt42b 1 c b8 pt43a 1 t c9 pt42a 1 t gnd gndio 1 b7 pt41b 1 c e9 pt40b 1 c a7 pt41a 1 t d8 pt40a 1 t vccio vccio1 1 a6 pt39b 1 pclkc1_0 c b6 pt39a 1 pclkt1_0 t e6 xres 1 f8 pt37b 0 pclkc0_0 c gnd gndio 0 e8 pt37a 0 pclkt0_0 t a5 pt36b 0 c a3 pt35b 0 c a4 pt36a 0 t vccio vccio0 0 b3 pt35a 0 t a2 pt34b 0 c c7 pt33b 0 c b2 pt34a 0 t d7 pt33a 0 t d6 pt32b 0 c gnd gndio 0 f7 pt31b 0 c lfe2-20e/20se logic signal connections: 256 fpbga (cont.) ball number ball function bank dual function differential
4-40 pinout information lattice semiconductor latticeecp2/m family data sheet c6 pt32a 0 t vccio vccio0 0 f6 pt31a 0 t c4 pt30b 0 c b4 pt30a 0 t gnd gndio 0 vcc vccio 0 d5 pt2b 0 vref2_0 c e5 pt2a 0 vref1_0 t g7 vcc - g9 vcc - h7 vcc - j10 vcc - k10 vcc - k8 vcc - g8 vccaux - h10 vccaux - j7 vccaux - k9 vccaux - c5 vccio 0 e7 vccio 0 c12 vccio 1 e10 vccio 1 e14 vccio 2 g12 vccio 2 k12 vccio 3 m14 vccio 3 m10 vccio 4 p12 vccio 4 m7 vccio 5 p5 vccio 5 k5 vccio 6 m3 vccio 6 e3 vccio 7 g5 vccio 7 t15 vccio 8 a1 gnd - a16 gnd - b12 gnd - b5 gnd - c8 gnd - e15 gnd - e2 gnd - h14 gnd - lfe2-20e/20se logic signal connections: 256 fpbga (cont.) ball number ball function bank dual function differential
4-41 pinout information lattice semiconductor latticeecp2/m family data sheet h8 gnd - h9 gnd - j3 gnd - j8 gnd - j9 gnd - m15 gnd - m2 gnd - p9 gnd - r12 gnd - r5 gnd - t1 gnd - t16 gnd - * supports true lvds outputs. ** these dedicated input pins can be used for gplls or gdlls within the respective quadrant. lfe2-20e/20se logic signal connections: 256 fpbga (cont.) ball number ball function bank dual function differential
4-42 pinout information lattice semiconductor latticeecp2/m family data sheet lfe2-12e/12se and lfe2-20e/20se logic signal connections: 484 fpbga lfe2-12e/12se lfe2-20e/20se ball number ball function bank dual function differential ball number ball function bank dual function differential e4 pl2a 7 vref2_7 t* e4 pl2a 7 vref2_7 t* e5 pl2b 7 vref1_7 c* e5 pl2b 7 vref1_7 c* - - - gnd gndio 7 e3 nc - e3 pl4a 7 t* f4 pl3a 7 t f4 pl5a 7 t f3 nc - f3 pl4b 7 c* f5 pl3b 7 c f5 pl5b 7 c e2 pl4a 7 t* e2 pl6a 7 t* g6 pl5a 7 t g6 pl7a 7 t e1 pl4b 7 c* e1 pl6b 7 c* g7 pl5b 7 c g7 pl7b 7 c gnd gndio 7 gnd gndio 7 f1 nc - f1 pl9a 7 t h4 nc - h4 pl8a 7 ldqs8 t* f2 nc - f2 pl9b 7 c h5 nc - h5 pl8b 7 c* g1 nc - g1 pl11a 7 t g3 nc - g3 pl10a 7 t* g2 nc - g2 pl11b 7 c - - - gnd gndio 7 g4 nc - g4 pl10b 7 c* j4 pl7a 7 t j4 pl13a 7 t h1 pl6a 7 h1 pl12a 7 j5 pl7b 7 c j5 pl13b 7 c l6 pl9a 7 t l6 pl15a 7 t j2 pl8a 7 t* j2 pl14a 7 t* l5 pl9b 7 c l5 pl15b 7 c j1 pl8b 7 c* j1 pl14b 7 c* k3 pl10a 7 ldqs10 t* k3 pl16a 7 ldqs16 t* gnd gndio 7 gnd gndio 7 k6 nc - k6 nc - k4 pl10b 7 c* k4 pl16b 7 c* k2 pl11a 7 t k2 pl17a 7 t k1 pl11b 7 c k1 pl17b 7 c l4 pl12a 7 t* l4 pl18a 7 t* l3 pl12b 7 c* l3 pl18b 7 c* gnd gndio 7 gnd gndio 7 l2 pl13a 7 pclkt7_0 t l2 pl19a 7 pclkt7_0 t l1 pl13b 7 pclkc7_0 c l1 pl19b 7 pclkc7_0 c m5 pl15a 6 pclkt6_0 t* m5 pl21a 6 pclkt6_0 t* m6 pl15b 6 pclkc6_0 c* m6 pl21b 6 pclkc6_0 c* m3 pl16a 6 vref2_6 t m3 pl22a 6 vref2_6 t m4 pl16b 6 vref1_6 c m4 pl22b 6 vref1_6 c n1 nc - n1 pl24a 6 t
4-43 pinout information lattice semiconductor latticeecp2/m family data sheet m2 nc - m2 pl23a 6 t* n2 nc - n2 pl24b 6 c m1 nc - m1 pl23b 6 c* gnd gndio 6 gnd gndio 6 n3 nc - n3 pl25a 6 ldqs25 t* n5 nc - n5 pl26a 6 t n4 nc - n4 pl25b 6 c* p5 nc - p5 pl26b 6 c p1 pl17a 6 llm0_gdllt_in_a** t* p1 pl27a 6 llm0_gdllt_in_a** t* p2 pl17b 6 llm0_gdllc_in_a** c* p2 pl27b 6 llm0_gdllc_in_a** c* p4 pl18a 6 llm0_gdllt_fb_a t p4 pl28a 6 llm0_gdllt_fb_a t gnd gndio 6 gnd gndio 6 r4 pl18b 6 llm0_gdllc_fb_a c r4 pl28b 6 llm0_gdllc_fb_a c n6 vcc - n6 vcc - p6 llm0_pllcap 6 p6 llm0_pllcap 6 r1 pl20a 6 llm0_gpllt_in_a** t* r1 pl30a 6 llm0_gpllt_in_a** t* r3 pl21a 6 llm0_gpllt_fb_a t r3 pl31a 6 llm0_gpllt_fb_a t r2 pl20b 6 llm0_gpllc_in_a** c* r2 pl30b 6 llm0_gpllc_in_a** c* t4 pl21b 6 llm0_gpllc_fb_a c t4 pl31b 6 llm0_gpllc_fb_a c t5 pl23a 6 t t5 pl33a 6 t t1 pl22a 6 t* t1 pl32a 6 t* t3 pl23b 6 c t3 pl33b 6 c gnd gndio 6 gnd gndio 6 t2 pl22b 6 c* t2 pl32b 6 c* v1 pl25a 6 t v1 pl39a 6 t - - - gnd gndio 6 v2 pl25b 6 c v2 pl39b 6 c u1 pl24a 6 t* u1 pl38a 6 t* u3 pl27a 6 t u3 pl41a 6 t u2 pl24b 6 c* u2 pl38b 6 c* u4 pl27b 6 c u4 pl41b 6 c gnd gndio 6 gnd gndio 6 r6 pl26a 6 t* r6 pl40a 6 t* r7 pl29a 6 t r7 pl43a 6 t t7 pl29b 6 c t7 pl43b 6 c t6 pl26b 6 c* t6 pl40b 6 c* aa2 pl31a 6 t aa2 pl45a 6 t y1 pl28a 6 ldqs28 t* y1 pl42a 6 ldqs42 t* aa1 pl31b 6 c aa1 pl45b 6 c gnd gndio 6 gnd gndio 6 w 1 pl28b 6 c* w 1 pl42b 6 c* v3 pl30b 6 c* v3 pl44b 6 c* v4 pl30a 6 t* v4 pl44a 6 t* u5 tdi - u5 tdi - lfe2-12e/12se and lfe2-20e/20se logic signal connections: 484 fpbga (cont.) lfe2-12e/12se lfe2-20e/20se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-44 pinout information lattice semiconductor latticeecp2/m family data sheet u7 tck - u7 tck - v6 tdo - v6 tdo - v5 tms - v5 tms - t8 vccj - t8 vccj - w 4 pb3a 5 t w 4 pb3a 5 t y3 pb2a 5 vref2_5 t y3 pb2a 5 vref2_5 t w 3 pb3b 5 c w 3 pb3b 5 c y2 pb2b 5 vref1_5 c y2 pb2b 5 vref1_5 c ab3 pb5a 5 t ab3 pb5a 5 t w 5 pb4a 5 t w 5 pb4a 5 t ab2 pb5b 5 c ab2 pb5b 5 c gnd gndio 5 gnd gndio 5 w 6 pb4b 5 c w 6 pb4b 5 c ab5 pb7a 5 t ab5 pb7a 5 t y4 pb6a 5 bdqs6 t y4 pb6a 5 bdqs6 t ab4 pb7b 5 c ab4 pb7b 5 c aa3 pb6b 5 c aa3 pb6b 5 c ab6 pb9a 5 t ab6 pb9a 5 t aa5 pb8a 5 t aa5 pb8a 5 t aa6 pb9b 5 c aa6 pb9b 5 c gnd gndio 5 gnd gndio 5 y5 pb8b 5 c y5 pb8b 5 c y6 pb12a 5 t y6 pb21a 5 t w 7 pb11a 5 t w 7 pb20a 5 t y7 pb12b 5 c y7 pb21b 5 c w 8 pb11b 5 c w 8 pb20b 5 c u8 pb14a 5 t u8 pb23a 5 t aa7 pb13a 5 t aa7 pb22a 5 t u9 pb14b 5 c u9 pb23b 5 c ab7 pb13b 5 c ab7 pb22b 5 c y8 pb16a 5 t y8 pb25a 5 t w 9 pb15a 5 bdqs15 t w 9 pb24a 5 bdqs24 t gnd gndio 5 gnd gndio 5 aa8 pb16b 5 c aa8 pb25b 5 c v9 pb15b 5 c v9 pb24b 5 c ab8 pb18a 5 t ab8 pb27a 5 t w 10 pb17a 5 t w 10 pb26a 5 t aa9 pb18b 5 c aa9 pb27b 5 c gnd gndio 5 gnd gndio 5 v10 pb17b 5 c v10 pb26b 5 c y10 pb21a 5 t y10 pb30a 5 t ab9 pb20a 5 t ab9 pb29a 5 t aa10 pb21b 5 c aa10 pb30b 5 c ab10 pb20b 5 c ab10 pb29b 5 c lfe2-12e/12se and lfe2-20e/20se logic signal connections: 484 fpbga (cont.) lfe2-12e/12se lfe2-20e/20se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-45 pinout information lattice semiconductor latticeecp2/m family data sheet ab11 pb23a 5 t ab11 pb32a 5 t u10 pb22a 5 t u10 pb31a 5 t aa11 pb23b 5 c aa11 pb32b 5 c gnd gndio 5 gnd gndio 5 u11 pb22b 5 c u11 pb31b 5 c ab12 pb25a 5 t ab12 pb34a 5 t y11 pb24a 5 bdqs24 t y11 pb33a 5 bdqs33 t aa12 pb25b 5 c aa12 pb34b 5 c w 11 pb24b 5 c w 11 pb33b 5 c ab13 pb26a 5 pclkt5_0 t ab13 pb35a 5 pclkt5_0 t ab14 pb26b 5 pclkc5_0 c ab14 pb35b 5 pclkc5_0 c gnd gndio 5 gnd gndio 5 y12 pb32a 4 t y12 pb41a 4 t w 12 pb32b 4 c w 12 pb41b 4 c u12 pb31a 4 pclkt4_0 t u12 pb40a 4 pclkt4_0 t v12 pb31b 4 pclkc4_0 c v12 pb40b 4 pclkc4_0 c u13 pb34a 4 t u13 pb43a 4 t aa13 pb33a 4 bdqs33 t aa13 pb42a 4 bdqs42 t gnd gndio 4 gnd gndio 4 u14 pb34b 4 c u14 pb43b 4 c y13 pb33b 4 c y13 pb42b 4 c ab16 pb36a 4 t ab16 pb45a 4 t ab15 pb35a 4 t ab15 pb44a 4 t ab17 pb36b 4 c ab17 pb45b 4 c aa14 pb35b 4 c aa14 pb44b 4 c w 13 pb37a 4 t w 13 pb46a 4 t gnd gndio 4 gnd gndio 4 w 14 pb37b 4 c w 14 pb46b 4 c ab18 pb39a 4 t ab18 pb48a 4 t ab19 pb39b 4 c ab19 pb48b 4 c y15 pb41a 4 t y15 pb50a 4 t v14 pb40a 4 t v14 pb49a 4 t aa15 pb41b 4 c aa15 pb50b 4 c gnd gndio 4 gnd gndio 4 w 15 pb40b 4 c w 15 pb49b 4 c ab20 pb43a 4 t ab20 pb52a 4 t aa16 pb42a 4 bdqs42 t aa16 pb51a 4 bdqs51 t ab21 pb43b 4 c ab21 pb52b 4 c aa17 pb42b 4 c aa17 pb51b 4 c y16 pb45a 4 t y16 pb54a 4 t u15 pb44a 4 t u15 pb53a 4 t w 16 pb45b 4 c w 16 pb54b 4 c u16 pb44b 4 c u16 pb53b 4 c aa18 pb46a 4 t aa18 pb55a 4 t lfe2-12e/12se and lfe2-20e/20se logic signal connections: 484 fpbga (cont.) lfe2-12e/12se lfe2-20e/20se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-46 pinout information lattice semiconductor latticeecp2/m family data sheet aa20 pb46b 4 c aa20 pb55b 4 c gnd gndio 4 gnd gndio 4 v16 pb49a 4 t v16 pb58a 4 t v17 pb49b 4 c v17 pb58b 4 c aa21 pb48a 4 t aa21 pb57a 4 t y19 pb51a 4 bdqs51 t y19 pb60a 4 bdqs60 t gnd gndio 4 gnd gndio 4 aa22 pb48b 4 c aa22 pb57b 4 c y20 pb51b 4 c y20 pb60b 4 c y18 pb50a 4 t y18 pb59a 4 t y21 pb53a 4 t y21 pb62a 4 t y17 pb50b 4 c y17 pb59b 4 c y22 pb53b 4 c y22 pb62b 4 c w 17 pb52a 4 t w 17 pb61a 4 t u18 pb54a 4 t u18 pb63a 4 t w 18 pb52b 4 c w 18 pb61b 4 c v18 pb54b 4 c v18 pb63b 4 c gnd gndio 4 gnd gndio 4 t15 pb55a 4 vref2_4 t t15 pb64a 4 vref2_4 t t16 pb55b 4 vref1_4 c t16 pb64b 4 vref1_4 c w 19 cfg2 8 w 19 cfg2 8 v19 cfg1 8 v19 cfg1 8 v20 programn 8 v20 programn 8 w 20 cfg0 8 w 20 cfg0 8 u22 pr28b 8 d1 c u22 pr42b 8 d1 c v22 initn 8 v22 initn 8 r16 pr30b 8 w riten c r16 pr44b 8 w riten c gnd gndio 8 gnd gndio 8 w 22 cclk 8 w 22 cclk 8 r17 pr30a 8 cs1n t r17 pr44a 8 cs1n t v21 done 8 v21 done 8 u19 pr29b 8 csn c u19 pr43b 8 csn c t17 pr26b 8 d5 c t17 pr40b 8 d5 c u20 pr29a 8 d0 t u20 pr43a 8 d0 t u21 pr28a 8 d2 t u21 pr42a 8 d2 t t18 pr26a 8 d6 t t18 pr40a 8 d6 t t20 pr27b 8 d3 c t20 pr41b 8 d3 c gnd gndio 8 gnd gndio 8 t21 pr25b 8 d7 c t21 pr39b 8 d7 c t19 pr27a 8 d4 t t19 pr41a 8 d4 t t22 pr25a 8 di t t22 pr39a 8 di t r18 pr24b 8 dout,cson c r18 pr38b 8 dout,cson c r19 pr24a 8 busy t r19 pr38a 8 busy t gnd gndio 8 gnd gndio 8 lfe2-12e/12se and lfe2-20e/20se logic signal connections: 484 fpbga (cont.) lfe2-12e/12se lfe2-20e/20se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-47 pinout information lattice semiconductor latticeecp2/m family data sheet p18 pr22b 3 c* p18 pr32b 3 c* gnd gndio 3 gnd gndio 3 r22 pr23b 3 c r22 pr33b 3 c p19 pr22a 3 t* p19 pr32a 3 t* r21 pr23a 3 t r21 pr33a 3 t r20 pr21b 3 rlm0_gpllc_fb_a c r20 pr31b 3 rlm0_gpllc_fb_a c p22 pr21a 3 rlm0_gpllt_fb_a t p22 pr31a 3 rlm0_gpllt_fb_a t p21 pr20b 3 rlm0_gpllc_in_a** c* p21 pr30b 3 rlm0_gpllc_in_a** c* n21 pr20a 3 rlm0_gpllt_in_a** t* n21 pr30a 3 rlm0_gpllt_in_a** t* n17 rlm0_pllcap 3 n17 rlm0_pllcap 3 n18 vcc - n18 vcc - n22 pr18b 3 rlm0_gdllc_fb_a c n22 pr28b 3 rlm0_gdllc_fb_a c m22 pr17b 3 rlm0_gdllc_in_a** c* m22 pr27b 3 rlm0_gdllc_in_a** c* gnd gndio 3 gnd gndio 3 n20 pr18a 3 rlm0_gdllt_fb_a t n20 pr28a 3 rlm0_gdllt_fb_a t m21 pr17a 3 rlm0_gdllt_in_a** t* m21 pr27a 3 rlm0_gdllt_in_a** t* n19 nc - n19 pr26b 3 c m19 nc - m19 pr26a 3 t j22 nc - j22 pr23b 3 c* - - - gnd gndio 3 l22 nc - l22 pr24b 3 c h22 nc - h22 pr23a 3 t* k22 nc - k22 pr24a 3 t m20 pr16b 3 vref2_3 c m20 pr22b 3 vref2_3 c l21 pr16a 3 vref1_3 t l21 pr22a 3 vref1_3 t k21 pr15b 3 pclkc3_0 c* k21 pr21b 3 pclkc3_0 c* j21 pr15a 3 pclkt3_0 t* j21 pr21a 3 pclkt3_0 t* m18 pr13b 2 pclkc2_0 c m18 pr19b 2 pclkc2_0 c gnd gndio 2 gnd gndio 2 l17 pr13a 2 pclkt2_0 t l17 pr19a 2 pclkt2_0 t l19 pr12b 2 c* l19 pr18b 2 c* k18 pr10b 2 c* k18 pr16b 2 c* l20 pr12a 2 t* l20 pr18a 2 t* k19 pr10a 2 rdqs10 t* k19 pr16a 2 rdqs16 t* gnd gndio 2 gnd gndio 2 l18 pr11b 2 c l18 pr17b 2 c k17 pr11a 2 t k17 pr17a 2 t j16 nc - j16 nc - j17 pr8b 2 c* j17 pr14b 2 c* g22 pr9b 2 c g22 pr15b 2 c j18 pr8a 2 t* j18 pr14a 2 t* f22 pr9a 2 t f22 pr15a 2 t h21 pr6b 2 c* h21 pr12b 2 c* k20 pr7b 2 c k20 pr13b 2 c lfe2-12e/12se and lfe2-20e/20se logic signal connections: 484 fpbga (cont.) lfe2-12e/12se lfe2-20e/20se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-48 pinout information lattice semiconductor latticeecp2/m family data sheet g21 pr6a 2 t* g21 pr12a 2 t* j19 pr7a 2 t j19 pr13a 2 t d22 nc - d22 pr10b 2 c* f21 nc - f21 pr11b 2 c - - - gnd gndio 2 e21 nc - e21 pr10a 2 t* e22 nc - e22 pr11a 2 t h19 nc - h19 pr8b 2 c* g20 nc - g20 pr9b 2 c g19 nc - g19 pr8a 2 rdqs8 t* f20 nc - f20 pr9a 2 t g17 pr5b 2 c g17 pr7b 2 c gnd gndio 2 gnd gndio 2 e20 pr4b 2 c* e20 pr6b 2 c* f19 pr5a 2 t f19 pr7a 2 t d20 pr4a 2 t* d20 pr6a 2 t* f18 pr3b 2 c f18 pr5b 2 c c21 nc - c21 pr4b 2 c* f16 pr3a 2 t f16 pr5a 2 t c22 nc - c22 pr4a 2 t* - - - gnd gndio 2 d19 pr2b 2 vref2_2 c* d19 pr2b 2 vref2_2 c* e19 pr2a 2 vref1_2 t* e19 pr2a 2 vref1_2 t* b21 pt55b 1 vref2_1 c b21 pt64b 1 vref2_1 c b22 pt55a 1 vref1_1 t b22 pt64a 1 vref1_1 t gnd gndio 1 gnd gndio 1 d18 pt53b 1 c d18 pt62b 1 c c20 pt54b 1 c c20 pt63b 1 c e18 pt53a 1 t e18 pt62a 1 t c19 pt54a 1 t c19 pt63a 1 t b20 pt52b 1 c b20 pt61b 1 c d17 pt51b 1 c d17 pt60b 1 c c18 pt51a 1 t c18 pt60a 1 t gnd gndio 1 gnd gndio 1 a19 pt52a 1 t a19 pt61a 1 t a18 pt49b 1 c a18 pt58b 1 c a21 pt50b 1 c a21 pt59b 1 c b18 pt49a 1 t b18 pt58a 1 t a20 pt50a 1 t a20 pt59a 1 t d16 pt47b 1 c d16 pt56b 1 c g16 pt48b 1 c g16 pt57b 1 c e16 pt47a 1 t e16 pt56a 1 t g15 pt48a 1 t g15 pt57a 1 t c17 pt46b 1 c c17 pt55b 1 c lfe2-12e/12se and lfe2-20e/20se logic signal connections: 484 fpbga (cont.) lfe2-12e/12se lfe2-20e/20se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-49 pinout information lattice semiconductor latticeecp2/m family data sheet gnd gndio 1 gnd gndio 1 c16 pt46a 1 t c16 pt55a 1 t a17 pt44b 1 c a17 pt53b 1 c b17 pt45b 1 c b17 pt54b 1 c a16 pt44a 1 t a16 pt53a 1 t b16 pt45a 1 t b16 pt54a 1 t e15 pt42b 1 c e15 pt51b 1 c c15 pt43b 1 c c15 pt52b 1 c f15 pt42a 1 t f15 pt51a 1 t gnd gndio 1 gnd gndio 1 d15 pt43a 1 t d15 pt52a 1 t b15 pt40b 1 c b15 pt49b 1 c a15 pt40a 1 t a15 pt49a 1 t a14 pt39a 1 t a14 pt48a 1 t b14 pt39b 1 c b14 pt48b 1 c d14 pt37b 1 c d14 pt46b 1 c e14 pt36b 1 c e14 pt45b 1 c c13 pt37a 1 t c13 pt46a 1 t gnd gndio 1 gnd gndio 1 f14 pt36a 1 t f14 pt45a 1 t a13 pt35b 1 c a13 pt44b 1 c e13 pt34b 1 c e13 pt43b 1 c b13 pt35a 1 t b13 pt44a 1 t d13 pt34a 1 t d13 pt43a 1 t e12 pt33b 1 c e12 pt42b 1 c d12 pt33a 1 t d12 pt42a 1 t gnd gndio 1 gnd gndio 1 a12 pt31b 1 c a12 pt40b 1 c b12 pt30b 1 pclkc1_0 c b12 pt39b 1 pclkc1_0 c a11 pt31a 1 t a11 pt40a 1 t c12 pt30a 1 pclkt1_0 t c12 pt39a 1 pclkt1_0 t f12 xres 1 f12 xres 1 gnd gndio 0 gnd gndio 0 b10 pt28b 0 pclkc0_0 c b10 pt37b 0 pclkc0_0 c b11 pt28a 0 pclkt0_0 t b11 pt37a 0 pclkt0_0 t c11 pt26b 0 c c11 pt35b 0 c a10 pt27b 0 c a10 pt36b 0 c c10 pt26a 0 t c10 pt35a 0 t a9 pt27a 0 t a9 pt36a 0 t a8 pt24b 0 c a8 pt33b 0 c e11 pt25b 0 c e11 pt34b 0 c a7 pt24a 0 t a7 pt33a 0 t f11 pt25a 0 t f11 pt34a 0 t b8 pt23b 0 c b8 pt32b 0 c lfe2-12e/12se and lfe2-20e/20se logic signal connections: 484 fpbga (cont.) lfe2-12e/12se lfe2-20e/20se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-50 pinout information lattice semiconductor latticeecp2/m family data sheet gnd gndio 0 gnd gndio 0 b9 pt23a 0 t b9 pt32a 0 t c8 pt20b 0 c c8 pt29b 0 c b7 pt21b 0 c b7 pt30b 0 c d8 pt20a 0 t d8 pt29a 0 t gnd gndio 0 gnd gndio 0 a6 pt21a 0 t a6 pt30a 0 t c7 pt17b 0 c c7 pt26b 0 c d10 pt18b 0 c d10 pt27b 0 c c6 pt17a 0 t c6 pt26a 0 t e10 pt18a 0 t e10 pt27a 0 t f10 pt15b 0 c f10 pt24b 0 c b6 pt16b 0 c b6 pt25b 0 c d9 pt15a 0 t d9 pt24a 0 t b5 pt16a 0 t b5 pt25a 0 t gnd gndio 0 gnd gndio 0 a5 pt13b 0 c a5 pt22b 0 c f9 pt14b 0 c f9 pt23b 0 c a4 pt13a 0 t a4 pt22a 0 t e9 pt14a 0 t e9 pt23a 0 t g8 pt11b 0 c g8 pt20b 0 c a3 pt12b 0 c a3 pt21b 0 c e8 pt11a 0 t e8 pt20a 0 t a2 pt12a 0 t a2 pt21a 0 t c3 pt10b 0 c c3 pt10b 0 c gnd gndio 0 gnd gndio 0 b3 pt10a 0 t b3 pt10a 0 t e7 pt8b 0 c e7 pt8b 0 c f8 pt9b 0 c f8 pt9b 0 c f7 pt8a 0 t f7 pt8a 0 t d7 pt9a 0 t d7 pt9a 0 t d4 pt6b 0 c d4 pt6b 0 c d5 pt7b 0 c d5 pt7b 0 c c4 pt6a 0 t c4 pt6a 0 t d6 pt7a 0 t d6 pt7a 0 t j7 pt4b 0 c j7 pt4b 0 c b2 pt5b 0 c b2 pt5b 0 c gnd gndio 0 gnd gndio 0 h7 pt4a 0 t h7 pt4a 0 t b1 pt5a 0 t b1 pt5a 0 t d1 pt2b 0 vref2_0 c d1 pt2b 0 vref2_0 c d3 pt3b 0 c d3 pt3b 0 c c1 pt2a 0 vref1_0 t c1 pt2a 0 vref1_0 t c2 pt3a 0 t c2 pt3a 0 t lfe2-12e/12se and lfe2-20e/20se logic signal connections: 484 fpbga (cont.) lfe2-12e/12se lfe2-20e/20se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-51 pinout information lattice semiconductor latticeecp2/m family data sheet j10 vcc - j10 vcc - j11 vcc - j11 vcc - j12 vcc - j12 vcc - j13 vcc - j13 vcc - k14 vcc - k14 vcc - k9 vcc - k9 vcc - l14 vcc - l14 vcc - l9 vcc - l9 vcc - m14 vcc - m14 vcc - m9 vcc - m9 vcc - n14 vcc - n14 vcc - n9 vcc - n9 vcc - p10 vcc - p10 vcc - p11 vcc - p11 vcc - p12 vcc - p12 vcc - p13 vcc - p13 vcc - g10 vccio0 0 g10 vccio0 0 g9 vccio0 0 g9 vccio0 0 h8 vccio0 0 h8 vccio0 0 h9 vccio0 0 h9 vccio0 0 g11 vccio1 1 g11 vccio1 1 g12 vccio1 1 g12 vccio1 1 g13 vccio1 1 g13 vccio1 1 g14 vccio1 1 g14 vccio1 1 h14 vccio2 2 h14 vccio2 2 h15 vccio2 2 h15 vccio2 2 j15 vccio2 2 j15 vccio2 2 k16 vccio2 2 k16 vccio2 2 l16 vccio3 3 l16 vccio3 3 m16 vccio3 3 m16 vccio3 3 n16 vccio3 3 n16 vccio3 3 p16 vccio3 3 p16 vccio3 3 r14 vccio4 4 r14 vccio4 4 t12 vccio4 4 t12 vccio4 4 t13 vccio4 4 t13 vccio4 4 t14 vccio4 4 t14 vccio4 4 r9 vccio5 5 r9 vccio5 5 t10 vccio5 5 t10 vccio5 5 t11 vccio5 5 t11 vccio5 5 t9 vccio5 5 t9 vccio5 5 n7 vccio6 6 n7 vccio6 6 p7 vccio6 6 p7 vccio6 6 p8 vccio6 6 p8 vccio6 6 r8 vccio6 6 r8 vccio6 6 lfe2-12e/12se and lfe2-20e/20se logic signal connections: 484 fpbga (cont.) lfe2-12e/12se lfe2-20e/20se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-52 pinout information lattice semiconductor latticeecp2/m family data sheet j8 vccio7 7 j8 vccio7 7 k7 vccio7 7 k7 vccio7 7 l7 vccio7 7 l7 vccio7 7 m7 vccio7 7 m7 vccio7 7 p15 vccio8 8 p15 vccio8 8 r15 vccio8 8 r15 vccio8 8 c5 vccaux - c5 vccaux - d11 vccaux - d11 vccaux - e17 vccaux - e17 vccaux - e6 vccaux - e6 vccaux - f13 vccaux - f13 vccaux - g18 vccaux - g18 vccaux - g5 vccaux - g5 vccaux - k5 vccaux - k5 vccaux - m17 vccaux - m17 vccaux - p17 vccaux - p17 vccaux - r5 vccaux - r5 vccaux - v11 vccaux - v11 vccaux - v13 vccaux - v13 vccaux - v15 vccaux - v15 vccaux - v7 vccaux - v7 vccaux - v8 vccaux - v8 vccaux - a1 gnd - a1 gnd - a22 gnd - a22 gnd - aa19 gnd - aa19 gnd - aa4 gnd - aa4 gnd - ab1 gnd - ab1 gnd - ab22 gnd - ab22 gnd - b19 gnd - b19 gnd - b4 gnd - b4 gnd - c14 gnd - c14 gnd - c9 gnd - c9 gnd - d2 gnd - d2 gnd - d21 gnd - d21 gnd - f17 gnd - f17 gnd - f6 gnd - f6 gnd - h10 gnd - h10 gnd - h11 gnd - h11 gnd - h12 gnd - h12 gnd - h13 gnd - h13 gnd - j14 gnd - j14 gnd - j20 gnd - j20 gnd - j3 gnd - j3 gnd - j9 gnd - j9 gnd - lfe2-12e/12se and lfe2-20e/20se logic signal connections: 484 fpbga (cont.) lfe2-12e/12se lfe2-20e/20se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-53 pinout information lattice semiconductor latticeecp2/m family data sheet k10 gnd - k10 gnd - k11 gnd - k11 gnd - k12 gnd - k12 gnd - k13 gnd - k13 gnd - k15 gnd - k15 gnd - k8 gnd - k8 gnd - l10 gnd - l10 gnd - l11 gnd - l11 gnd - l12 gnd - l12 gnd - l13 gnd - l13 gnd - l15 gnd - l15 gnd - l8 gnd - l8 gnd - m10 gnd - m10 gnd - m11 gnd - m11 gnd - m12 gnd - m12 gnd - m13 gnd - m13 gnd - m15 gnd - m15 gnd - m8 gnd - m8 gnd - n10 gnd - n10 gnd - n11 gnd - n11 gnd - n12 gnd - n12 gnd - n13 gnd - n13 gnd - n15 gnd - n15 gnd - n8 gnd - n8 gnd - p14 gnd - p14 gnd - p20 gnd - p20 gnd - p3 gnd - p3 gnd - p9 gnd - p9 gnd - r10 gnd - r10 gnd - r11 gnd - r11 gnd - r12 gnd - r12 gnd - r13 gnd - r13 gnd - u17 gnd - u17 gnd - u6 gnd - u6 gnd - w 2 gnd - w 2 gnd - w 21 gnd - w 21 gnd - y14 gnd - y14 gnd - y9 gnd - y9 gnd - h6 nc - h6 nc - j6 nc - j6 nc - h3 nc - h3 nc - h2 nc - h2 nc - h17 nc - h17 nc - h16 nc - h16 nc - lfe2-12e/12se and lfe2-20e/20se logic signal connections: 484 fpbga (cont.) lfe2-12e/12se lfe2-20e/20se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-54 pinout information lattice semiconductor latticeecp2/m family data sheet h20 nc - h20 nc - h18 nc - h18 nc - * supports true lvds outputs. ** these dedicated input pins can be used for gplls or gdlls within the respective quadrant. lfe2-12e/12se and lfe2-20e/20se logic signal connections: 484 fpbga (cont.) lfe2-12e/12se lfe2-20e/20se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-55 pinout information lattice semiconductor latticeecp2/m family data sheet lfe2-35e/35se and lfe2-50e/50se logic signal connections: 484 fpbga lfe2-35e/35se lfe2-50e/50se ball number ball function bank dual function differential ball number ball function bank dual function differential e4 pl2a 7 vref2_7 t* e4 pl2a 7 vref2_7 t* e5 pl2b 7 vref1_7 c* e5 pl2b 7 vref1_7 c* gnd gndio 7 gnd gndio 7 e3 pl10a 7 t* e3 pl12a 7 t* f4 pl11a 7 t f4 pl13a 7 t f3 pl10b 7 c* f3 pl12b 7 c* f5 pl11b 7 c f5 pl13b 7 c e2 pl12a 7 t* e2 pl14a 7 t* g6 pl13a 7 t g6 pl15a 7 t e1 pl12b 7 c* e1 pl14b 7 c* g7 pl13b 7 c g7 pl15b 7 c gnd gndio 7 gnd gndio 7 f1 pl15a 7 t f1 pl17a 7 t h4 pl14a 7 ldqs14 t* h4 pl16a 7 ldqs16 t* f2 pl15b 7 c f2 pl17b 7 c h5 pl14b 7 c* h5 pl16b 7 c* g1 pl17a 7 t g1 pl19a 7 t g3 pl16a 7 t* g3 pl18a 7 t* g2 pl17b 7 c g2 pl19b 7 c gnd gndio 7 gnd gndio 7 g4 pl16b 7 c* g4 pl18b 7 c* j4 pl19a 7 t j4 pl38a 7 t h1 pl18a 7 h1 pl37a 7 j5 pl19b 7 c j5 pl38b 7 c l6 pl21a 7 t l6 pl40a 7 t j2 pl20a 7 t* j2 pl39a 7 t* l5 pl21b 7 c l5 pl40b 7 c j1 pl20b 7 c* j1 pl39b 7 c* k3 pl22a 7 ldqs22 t* k3 pl41a 7 ldqs41 t* gnd gndio 7 gnd gndio 7 k6 nc - k6 vccpll - k4 pl22b 7 c* k4 pl41b 7 c* k2 pl23a 7 t k2 pl42a 7 t k1 pl23b 7 c k1 pl42b 7 c l4 pl24a 7 t* l4 pl43a 7 t* l3 pl24b 7 c* l3 pl43b 7 c* gnd gndio 7 gnd gndio 7 l2 pl25a 7 pclkt7_0 t l2 pl44a 7 pclkt7_0 t l1 pl25b 7 pclkc7_0 c l1 pl44b 7 pclkc7_0 c m5 pl27a 6 pclkt6_0 t* m5 pl46a 6 pclkt6_0 t* m6 pl27b 6 pclkc6_0 c* m6 pl46b 6 pclkc6_0 c* m3 pl28a 6 vref2_6 t m3 pl47a 6 vref2_6 t m4 pl28b 6 vref1_6 c m4 pl47b 6 vref1_6 c n1 pl30a 6 t n1 pl49a 6 t
4-56 pinout information lattice semiconductor latticeecp2/m family data sheet m2 pl29a 6 t* m2 pl48a 6 t* n2 pl30b 6 c n2 pl49b 6 c m1 pl29b 6 c* m1 pl48b 6 c* gnd gndio 6 gnd gndio 6 n3 pl39a 6 ldqs39 t* n3 pl58a 6 ldqs58 t* n5 pl40a 6 t n5 pl59a 6 t n4 pl39b 6 c* n4 pl58b 6 c* p5 pl40b 6 c p5 pl59b 6 c p1 pl41a 6 llm0_gdllt_in_a** t* p1 pl60a 6 llm0_gdllt_in_a** t* p2 pl41b 6 llm0_gdllc_in_a** c* p2 pl60b 6 llm0_gdllc_in_a** c* p4 pl42a 6 llm0_gdllt_fb_a t p4 pl61a 6 llm0_gdllt_fb_a t gnd gndio 6 gnd gndio 6 r4 pl42b 6 llm0_gdllc_fb_a c r4 pl61b 6 llm0_gdllc_fb_d c n6 vccpll - n6 vccpll - p6 llm0_pllcap 6 p6 llm0_pllcap 6 r1 pl44a 6 llm0_gpllt_in_a** t* r1 pl63a 6 llm0_gpllt_in_a** t* r3 pl45a 6 llm0_gpllt_fb_a t r3 pl64a 6 llm0_gpllt_fb_a t r2 pl44b 6 llm0_gpllc_in_a** c* r2 pl63b 6 llm0_gpllc_in_a** c* t4 pl45b 6 llm0_gpllc_fb_a c t4 pl64b 6 llm0_gpllc_fb_a c t5 pl47a 6 t t5 pl66a 6 t t1 pl46a 6 t* t1 pl65a 6 t* t3 pl47b 6 c t3 pl66b 6 c gnd gndio 6 gnd gndio 6 t2 pl46b 6 c* t2 pl65b 6 c* v1 pl53a 6 t v1 pl72a 6 t gnd gndio 6 gnd gndio 6 v2 pl53b 6 c v2 pl72b 6 c u1 pl52a 6 t* u1 pl71a 6 t* u3 pl55a 6 t u3 pl74a 6 t u2 pl52b 6 c* u2 pl71b 6 c* u4 pl55b 6 c u4 pl74b 6 c gnd gndio 6 gnd gndio 6 r6 pl54a 6 t* r6 pl73a 6 t* r7 pl57a 6 t r7 pl76a 6 t t7 pl57b 6 c t7 pl76b 6 c t6 pl54b 6 c* t6 pl73b 6 c* aa2 pl59a 6 t aa2 pl78a 6 t y1 pl56a 6 ldqs56 t* y1 pl75a 6 ldqs75 t* aa1 pl59b 6 c aa1 pl78b 6 c gnd gndio 6 gnd gndio 6 w 1 pl56b 6 c* w 1 pl75b 6 c* v3 pl58b 6 c* v3 pl77b 6 c* v4 pl58a 6 t* v4 pl77a 6 t* u5 tdi - u5 tdi - lfe2-35e/35se and lfe2-50e/50se logic signal connections: 484 fpbga (cont.) lfe2-35e/35se lfe2-50e/50se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-57 pinout information lattice semiconductor latticeecp2/m family data sheet u7 tck - u7 tck - v6 tdo - v6 tdo - v5 tms - v5 tms - t8 vccj - t8 vccj - w 4 pb3a 5 t w 4 pb3a 5 t y3 pb2a 5 vref2_5 t y3 pb2a 5 vref2_5 t w 3 pb3b 5 c w 3 pb3b 5 c y2 pb2b 5 vref1_5 c y2 pb2b 5 vref1_5 c ab3 pb5a 5 t ab3 pb5a 5 t w 5 pb4a 5 t w 5 pb4a 5 t ab2 pb5b 5 c ab2 pb5b 5 c gnd gndio 5 gnd gndio 5 w 6 pb4b 5 c w 6 pb4b 5 c ab5 pb7a 5 t ab5 pb7a 5 t y4 pb6a 5 bdqs6 t y4 pb6a 5 bdqs6 t ab4 pb7b 5 c ab4 pb7b 5 c aa3 pb6b 5 c aa3 pb6b 5 c ab6 pb9a 5 t ab6 pb9a 5 t aa5 pb8a 5 t aa5 pb8a 5 t aa6 pb9b 5 c aa6 pb9b 5 c gnd gndio 5 gnd gndio 5 y5 pb8b 5 c y5 pb8b 5 c y6 pb21a 5 t y6 pb30a 5 t w 7 pb20a 5 t w 7 pb29a 5 t y7 pb21b 5 c y7 pb30b 5 c w 8 pb20b 5 c w 8 pb29b 5 c u8 pb23a 5 t u8 pb32a 5 t aa7 pb22a 5 t aa7 pb31a 5 t u9 pb23b 5 c u9 pb32b 5 c ab7 pb22b 5 c ab7 pb31b 5 c y8 pb25a 5 t y8 pb34a 5 t w 9 pb24a 5 bdqs24 t w 9 pb33a 5 bdqs33 t gnd gndio 5 gnd gndio 5 aa8 pb25b 5 c aa8 pb34b 5 c v9 pb24b 5 c v9 pb33b 5 c ab8 pb27a 5 t ab8 pb36a 5 t w 10 pb26a 5 t w 10 pb35a 5 t aa9 pb27b 5 c aa9 pb36b 5 c gnd gndio 5 gnd gndio 5 v10 pb26b 5 c v10 pb35b 5 c y10 pb30a 5 t y10 pb39a 5 t ab9 pb29a 5 t ab9 pb38a 5 t aa10 pb30b 5 c ab10 pb38b 5 c ab10 pb29b 5 c aa10 pb39b 5 c lfe2-35e/35se and lfe2-50e/50se logic signal connections: 484 fpbga (cont.) lfe2-35e/35se lfe2-50e/50se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-58 pinout information lattice semiconductor latticeecp2/m family data sheet ab11 pb32a 5 t ab11 pb41a 5 t u10 pb31a 5 t u10 pb40a 5 t aa11 pb32b 5 c aa11 pb41b 5 c gnd gndio 5 gnd gndio 5 u11 pb31b 5 c u11 pb40b 5 c ab12 pb34a 5 t ab12 pb43a 5 t y11 pb33a 5 bdqs33 t y11 pb42a 5 bdqs42 t aa12 pb34b 5 c aa12 pb43b 5 c w 11 pb33b 5 c w 11 pb42b 5 c ab13 pb35a 5 pclkt5_0 t ab13 pb44a 5 pclkt5_0 t ab14 pb35b 5 pclkc5_0 c ab14 pb44b 5 pclkc5_0 c gnd gndio 5 gnd gndio 5 y12 pb41a 4 t y12 pb50a 4 t w 12 pb41b 4 c w 12 pb50b 4 c u12 pb40a 4 pclkt4_0 t u12 pb49a 4 pclkt4_0 t v12 pb40b 4 pclkc4_0 c v12 pb49b 4 pclkc4_0 c u13 pb43a 4 t u13 pb52a 4 t aa13 pb42a 4 bdqs42 t aa13 pb51a 4 bdqs51 t gnd gndio 4 gnd gndio 4 u14 pb43b 4 c u14 pb52b 4 c y13 pb42b 4 c y13 pb51b 4 c ab16 pb45a 4 t ab16 pb54a 4 t ab15 pb44a 4 t ab15 pb53a 4 t ab17 pb45b 4 c ab17 pb54b 4 c aa14 pb44b 4 c aa14 pb53b 4 c w 13 pb46a 4 t w 13 pb55a 4 t gnd gndio 4 gnd gndio 4 w 14 pb46b 4 c w 14 pb55b 4 c ab18 pb48a 4 t ab18 pb57a 4 t ab19 pb48b 4 c ab19 pb57b 4 c y15 pb50a 4 t y15 pb59a 4 t v14 pb49a 4 t v14 pb58a 4 t aa15 pb50b 4 c aa15 pb59b 4 c gnd gndio 4 gnd gndio 4 w 15 pb49b 4 c w 15 pb58b 4 c ab20 pb52a 4 t ab20 pb61a 4 t aa16 pb51a 4 bdqs51 t aa16 pb60a 4 bdqs60 t ab21 pb52b 4 c ab21 pb61b 4 c aa17 pb51b 4 c aa17 pb60b 4 c y16 pb54a 4 t y16 pb63a 4 t u15 pb53a 4 t u15 pb62a 4 t w 16 pb54b 4 c w 16 pb63b 4 c u16 pb53b 4 c u16 pb62b 4 c aa18 pb55a 4 t aa18 pb64a 4 t lfe2-35e/35se and lfe2-50e/50se logic signal connections: 484 fpbga (cont.) lfe2-35e/35se lfe2-50e/50se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-59 pinout information lattice semiconductor latticeecp2/m family data sheet aa20 pb55b 4 c aa20 pb64b 4 c gnd gndio 4 gnd gndio 4 v16 pb67a 4 t v16 pb76a 4 t v17 pb67b 4 c v17 pb76b 4 c aa21 pb66a 4 t aa21 pb75a 4 t y19 pb69a 4 bdqs69 t y19 pb78a 4 bdqs78 t gnd gndio 4 gnd gndio 4 aa22 pb66b 4 c aa22 pb75b 4 c y20 pb69b 4 c y20 pb78b 4 c y18 pb68a 4 t y18 pb77a 4 t y21 pb71a 4 t y21 pb80a 4 t y17 pb68b 4 c y17 pb77b 4 c y22 pb71b 4 c y22 pb80b 4 c w 17 pb70a 4 t w 17 pb79a 4 t u18 pb72a 4 t u18 pb81a 4 t w 18 pb70b 4 c w 18 pb79b 4 c v18 pb72b 4 c v18 pb81b 4 c gnd gndio 4 gnd gndio 4 t15 pb73a 4 vref2_4 t t15 pb82a 4 vref2_4 t t16 pb73b 4 vref1_4 c t16 pb82b 4 vref1_4 c w 19 cfg2 8 w 19 cfg2 8 v19 cfg1 8 v19 cfg1 8 v20 programn 8 v20 programn 8 w 20 cfg0 8 w 20 cfg0 8 u22 pr56b 8 d1 c u22 pr75b 8 d1 c v22 initn 8 v22 initn 8 r16 pr58b 8 w riten c r16 pr77b 8 w riten c gnd gndio 8 gnd gndio 8 w 22 cclk 8 w 22 cclk 8 r17 pr58a 8 cs1n t r17 pr77a 8 cs1n t v21 done 8 v21 done 8 u19 pr57b 8 csn c u19 pr76b 8 csn c t17 pr54b 8 d5 c t17 pr73b 8 d5 c u20 pr57a 8 d0 t u20 pr76a 8 d0 t u21 pr56a 8 d2 t u21 pr75a 8 d2 t t18 pr54a 8 d6 t t18 pr73a 8 d6 t t20 pr55b 8 d3 c t20 pr74b 8 d3 c gnd gndio 8 gnd gndio 8 t21 pr53b 8 d7 c t21 pr72b 8 d7 c t19 pr55a 8 d4 t t19 pr74a 8 d4 t t22 pr53a 8 di t t22 pr72a 8 di t r18 pr52b 8 dout_cson c r18 pr71b 8 dout,cson c r19 pr52a 8 busy t r19 pr71a 8 busy t gnd gndio 8 gnd gndio 8 lfe2-35e/35se and lfe2-50e/50se logic signal connections: 484 fpbga (cont.) lfe2-35e/35se lfe2-50e/50se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-60 pinout information lattice semiconductor latticeecp2/m family data sheet p18 pr46b 3 c* p18 pr65b 3 c* gnd gndio 3 gnd gndio 3 r22 pr47b 3 c r22 pr66b 3 c p19 pr46a 3 t* p19 pr65a 3 t* r21 pr47a 3 t r21 pr66a 3 t r20 pr45b 3 rlm0_gpllc_fb_a c r20 pr64b 3 rlm0_gpllc_fb_a c p22 pr45a 3 rlm0_gpllt_fb_a t p22 pr64a 3 rlm0_gpllt_fb_a t p21 pr44b 3 rlm0_gpllc_in_a** c* p21 pr63b 3 rlm0_gpllc_in_a** c* n21 pr44a 3 rlm0_gpllt_in_a** t* n21 pr63a 3 rlm0_gpllt_in_a** t* n17 rlm0_pllcap 3 n17 rlm0_pllcap 3 n18 vccpll - n18 vccpll - n22 pr42b 3 rlm0_gdllc_fb_a c n22 pr61b 3 rlm0_gdllc_fb_a c m22 pr41b 3 rlm0_gdllc_in_a** c* m22 pr60b 3 rlm0_gdllc_in_a** c* gnd gndio 3 gnd gndio 3 n20 pr42a 3 rlm0_gdllt_fb_a t n20 pr61a 3 rlm0_gdllt_fb_a t m21 pr41a 3 rlm0_gdllt_in_a** t* m21 pr60a 3 rlm0_gdllt_in_a** t* n19 pr40b 3 c n19 pr59b 3 c m19 pr40a 3 t m19 pr59a 3 t j22 pr29b 3 c* j22 pr48b 3 c* gnd gndio 3 gnd gndio 3 l22 pr30b 3 c l22 pr49b 3 c h22 pr29a 3 t* h22 pr48a 3 t* k22 pr30a 3 t k22 pr49a 3 t m20 pr28b 3 vref2_3 c m20 pr47b 3 vref2_3 c l21 pr28a 3 vref1_3 t l21 pr47a 3 vref1_3 t k21 pr27b 3 pclkc3_0 c* k21 pr46b 3 pclkc3_0 c* j21 pr27a 3 pclkt3_0 t* j21 pr46a 3 pclkt3_0 t* m18 pr25b 2 pclkc2_0 c m18 pr44b 2 pclkc2_0 c gnd gndio 2 gnd gndio 2 l17 pr25a 2 pclkt2_0 t l17 pr44a 2 pclkt2_0 t l19 pr24b 2 c* l19 pr43b 2 c* k18 pr22b 2 c* k18 pr41b 2 c* l20 pr24a 2 t* l20 pr43a 2 t* k19 pr22a 2 rdqs22 t* k19 pr41a 2 rdqs41 t* gnd gndio 2 gnd gndio 2 l18 pr23b 2 c l18 pr42b 2 c k17 pr23a 2 t k17 pr42a 2 t j16 nc - j16 vccpll - j17 pr20b 2 c* j17 pr39b 2 c* g22 pr21b 2 c g22 pr40b 2 c j18 pr20a 2 t* j18 pr39a 2 t* f22 pr21a 2 t f22 pr40a 2 t h21 pr18b 2 c* h21 pr37b 2 c* k20 pr19b 2 c k20 pr38b 2 c lfe2-35e/35se and lfe2-50e/50se logic signal connections: 484 fpbga (cont.) lfe2-35e/35se lfe2-50e/50se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-61 pinout information lattice semiconductor latticeecp2/m family data sheet g21 pr18a 2 t* g21 pr37a 2 t* j19 pr19a 2 t j19 pr38a 2 t d22 pr16b 2 c* d22 pr18b 2 c* f21 pr17b 2 c f21 pr19b 2 c gnd gndio 2 gnd gndio 2 e21 pr16a 2 t* e21 pr18a 2 t* e22 pr17a 2 t e22 pr19a 2 t h19 pr14b 2 c* h19 pr16b 2 c* g20 pr15b 2 c g20 pr17b 2 c g19 pr14a 2 rdqs14 t* g19 pr16a 2 rdqs16 t* f20 pr15a 2 t f20 pr17a 2 t g17 pr13b 2 c g17 pr15b 2 c gnd gndio 2 gnd gndio 2 e20 pr12b 2 c* e20 pr14b 2 c* f19 pr13a 2 t f19 pr15a 2 t d20 pr12a 2 t* d20 pr14a 2 t* f18 pr11b 2 c f18 pr13b 2 c c21 pr10b 2 c* c21 pr12b 2 c* f16 pr11a 2 t f16 pr13a 2 t c22 pr10a 2 t* c22 pr12a 2 t* gnd gndio 2 gnd gndio 2 d19 pr2b 2 vref2_2 c* d19 pr2b 2 vref2_2 c* e19 pr2a 2 vref1_2 t* e19 pr2a 2 vref1_2 t* b21 pt73b 1 vref2_1 c b21 pt82b 1 vref2_1 c b22 pt73a 1 vref1_1 t b22 pt82a 1 vref1_1 t gnd gndio 1 gnd gndio 1 d18 pt71b 1 c d18 pt80b 1 c c20 pt72b 1 c c20 pt81b 1 c e18 pt71a 1 t e18 pt80a 1 t c19 pt72a 1 t c19 pt81a 1 t b20 pt70b 1 c b20 pt79b 1 c d17 pt69b 1 c d17 pt78b 1 c c18 pt69a 1 t c18 pt78a 1 t gnd gndio 1 gnd gndio 1 a19 pt70a 1 t a19 pt79a 1 t a18 pt67b 1 c a18 pt76b 1 c a21 pt68b 1 c a21 pt77b 1 c b18 pt67a 1 t b18 pt76a 1 t a20 pt68a 1 t a20 pt77a 1 t d16 pt65b 1 c d16 pt74b 1 c g16 pt66b 1 c g16 pt75b 1 c e16 pt65a 1 t e16 pt74a 1 t g15 pt66a 1 t g15 pt75a 1 t c17 pt55b 1 c c17 pt64b 1 c lfe2-35e/35se and lfe2-50e/50se logic signal connections: 484 fpbga (cont.) lfe2-35e/35se lfe2-50e/50se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-62 pinout information lattice semiconductor latticeecp2/m family data sheet gnd gndio 1 gnd gndio 1 c16 pt55a 1 t c16 pt64a 1 t a17 pt53b 1 c a17 pt62b 1 c b17 pt54b 1 c b17 pt63b 1 c a16 pt53a 1 t a16 pt62a 1 t b16 pt54a 1 t b16 pt63a 1 t e15 pt51b 1 c e15 pt60b 1 c c15 pt52b 1 c c15 pt61b 1 c f15 pt51a 1 t f15 pt60a 1 t gnd gndio 1 gnd gndio 1 d15 pt52a 1 t d15 pt61a 1 t b15 pt49b 1 c b15 pt58b 1 c a15 pt49a 1 t a15 pt58a 1 t a14 pt48a 1 t a14 pt57a 1 t b14 pt48b 1 c b14 pt57b 1 c d14 pt46b 1 c d14 pt55b 1 c e14 pt45b 1 c e14 pt54b 1 c c13 pt46a 1 t c13 pt55a 1 t gnd gndio 1 gnd gndio 1 f14 pt45a 1 t f14 pt54a 1 t a13 pt44b 1 c a13 pt53b 1 c e13 pt43b 1 c e13 pt52b 1 c b13 pt44a 1 t b13 pt53a 1 t d13 pt43a 1 t d13 pt52a 1 t e12 pt42b 1 c e12 pt51b 1 c d12 pt42a 1 t d12 pt51a 1 t gnd gndio 1 gnd gndio 1 a12 pt40b 1 c a12 pt49b 1 c b12 pt39b 1 pclkc1_0 c b12 pt48b 1 pclkc1_0 c a11 pt40a 1 t a11 pt49a 1 t c12 pt39a 1 pclkt1_0 t c12 pt48a 1 pclkt1_0 t f12 xres 1 f12 xres 1 gnd gndio 0 gnd gndio 0 b10 pt37b 0 pclkc0_0 c b10 pt46b 0 pclkc0_0 c b11 pt37a 0 pclkt0_0 t b11 pt46a 0 pclkt0_0 t c11 pt35b 0 c c11 pt44b 0 c a10 pt36b 0 c a10 pt45b 0 c c10 pt35a 0 t c10 pt44a 0 t a9 pt36a 0 t a9 pt45a 0 t a8 pt33b 0 c a8 pt42b 0 c e11 pt34b 0 c e11 pt43b 0 c a7 pt33a 0 t a7 pt42a 0 t f11 pt34a 0 t f11 pt43a 0 t b8 pt32b 0 c b8 pt41b 0 c lfe2-35e/35se and lfe2-50e/50se logic signal connections: 484 fpbga (cont.) lfe2-35e/35se lfe2-50e/50se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-63 pinout information lattice semiconductor latticeecp2/m family data sheet gnd gndio 0 gnd gndio 0 b9 pt32a 0 t b9 pt41a 0 t c8 pt29b 0 c c8 pt38b 0 c b7 pt30b 0 c b7 pt39b 0 c d8 pt29a 0 t d8 pt38a 0 t gnd gndio 0 gnd gndio 0 a6 pt30a 0 t a6 pt39a 0 t c7 pt26b 0 c c7 pt35b 0 c d10 pt27b 0 c d10 pt36b 0 c c6 pt26a 0 t c6 pt35a 0 t e10 pt27a 0 t e10 pt36a 0 t f10 pt24b 0 c f10 pt33b 0 c b6 pt25b 0 c b6 pt34b 0 c d9 pt24a 0 t d9 pt33a 0 t b5 pt25a 0 t b5 pt34a 0 t gnd gndio 0 gnd gndio 0 a5 pt22b 0 c a5 pt31b 0 c f9 pt23b 0 c f9 pt32b 0 c a4 pt22a 0 t a4 pt31a 0 t e9 pt23a 0 t e9 pt32a 0 t g8 pt20b 0 c g8 pt29b 0 c a3 pt21b 0 c a3 pt30b 0 c e8 pt20a 0 t e8 pt29a 0 t a2 pt21a 0 t a2 pt30a 0 t c3 pt10b 0 c c3 pt10b 0 c gnd gndio 0 gnd gndio 0 b3 pt10a 0 t b3 pt10a 0 t e7 pt8b 0 c e7 pt8b 0 c f8 pt9b 0 c f8 pt9b 0 c f7 pt8a 0 t f7 pt8a 0 t d7 pt9a 0 t d7 pt9a 0 t d4 pt6b 0 c d4 pt6b 0 c d5 pt7b 0 c d5 pt7b 0 c c4 pt6a 0 t c4 pt6a 0 t d6 pt7a 0 t d6 pt7a 0 t j7 pt4b 0 c j7 pt4b 0 c b2 pt5b 0 c b2 pt5b 0 c gnd gndio 0 gnd gndio 0 h7 pt4a 0 t h7 pt4a 0 t b1 pt5a 0 t b1 pt5a 0 t d1 pt2b 0 vref2_0 c d1 pt2b 0 vref2_0 c d3 pt3b 0 c d3 pt3b 0 c c1 pt2a 0 vref1_0 t c1 pt2a 0 vref1_0 t c2 pt3a 0 t c2 pt3a 0 t lfe2-35e/35se and lfe2-50e/50se logic signal connections: 484 fpbga (cont.) lfe2-35e/35se lfe2-50e/50se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-64 pinout information lattice semiconductor latticeecp2/m family data sheet j10 vcc - j10 vcc - j11 vcc - j11 vcc - j12 vcc - j12 vcc - j13 vcc - j13 vcc - k14 vcc - k14 vcc - k9 vcc - k9 vcc - l14 vcc - l14 vcc - l9 vcc - l9 vcc - m14 vcc - m14 vcc - m9 vcc - m9 vcc - n14 vcc - n14 vcc - n9 vcc - n9 vcc - p10 vcc - p10 vcc - p11 vcc - p11 vcc - p12 vcc - p12 vcc - p13 vcc - p13 vcc - g10 vccio0 0 g10 vccio0 0 g9 vccio0 0 g9 vccio0 0 h8 vccio0 0 h8 vccio0 0 h9 vccio0 0 h9 vccio0 0 g11 vccio1 1 g11 vccio1 1 g12 vccio1 1 g12 vccio1 1 g13 vccio1 1 g13 vccio1 1 g14 vccio1 1 g14 vccio1 1 h14 vccio2 2 h14 vccio2 2 h15 vccio2 2 h15 vccio2 2 j15 vccio2 2 j15 vccio2 2 k16 vccio2 2 k16 vccio2 2 l16 vccio3 3 l16 vccio3 3 m16 vccio3 3 m16 vccio3 3 n16 vccio3 3 n16 vccio3 3 p16 vccio3 3 p16 vccio3 3 r14 vccio4 4 r14 vccio4 4 t12 vccio4 4 t12 vccio4 4 t13 vccio4 4 t13 vccio4 4 t14 vccio4 4 t14 vccio4 4 r9 vccio5 5 r9 vccio5 5 t10 vccio5 5 t10 vccio5 5 t11 vccio5 5 t11 vccio5 5 t9 vccio5 5 t9 vccio5 5 n7 vccio6 6 n7 vccio6 6 p7 vccio6 6 p7 vccio6 6 p8 vccio6 6 p8 vccio6 6 r8 vccio6 6 r8 vccio6 6 lfe2-35e/35se and lfe2-50e/50se logic signal connections: 484 fpbga (cont.) lfe2-35e/35se lfe2-50e/50se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-65 pinout information lattice semiconductor latticeecp2/m family data sheet j8 vccio7 7 j8 vccio7 7 k7 vccio7 7 k7 vccio7 7 l7 vccio7 7 l7 vccio7 7 m7 vccio7 7 m7 vccio7 7 p15 vccio8 8 p15 vccio8 8 r15 vccio8 8 r15 vccio8 8 c5 vccaux - c5 vccaux - d11 vccaux - d11 vccaux - e17 vccaux - e17 vccaux - e6 vccaux - e6 vccaux - f13 vccaux - f13 vccaux - g18 vccaux - g18 vccaux - g5 vccaux - g5 vccaux - k5 vccaux - k5 vccaux - m17 vccaux - m17 vccaux - p17 vccaux - p17 vccaux - r5 vccaux - r5 vccaux - v11 vccaux - v11 vccaux - v13 vccaux - v13 vccaux - v15 vccaux - v15 vccaux - v7 vccaux - v7 vccaux - v8 vccaux - v8 vccaux - a1 gnd - a1 gnd - a22 gnd - a22 gnd - aa19 gnd - aa19 gnd - aa4 gnd - aa4 gnd - ab1 gnd - ab1 gnd - ab22 gnd - ab22 gnd - b19 gnd - b19 gnd - b4 gnd - b4 gnd - c14 gnd - c14 gnd - c9 gnd - c9 gnd - d2 gnd - d2 gnd - d21 gnd - d21 gnd - f17 gnd - f17 gnd - f6 gnd - f6 gnd - h10 gnd - h10 gnd - h11 gnd - h11 gnd - h12 gnd - h12 gnd - h13 gnd - h13 gnd - j14 gnd - j14 gnd - j20 gnd - j20 gnd - j3 gnd - j3 gnd - j9 gnd - j9 gnd - lfe2-35e/35se and lfe2-50e/50se logic signal connections: 484 fpbga (cont.) lfe2-35e/35se lfe2-50e/50se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-66 pinout information lattice semiconductor latticeecp2/m family data sheet k10 gnd - k10 gnd - k11 gnd - k11 gnd - k12 gnd - k12 gnd - k13 gnd - k13 gnd - k15 gnd - k15 gnd - k8 gnd - k8 gnd - l10 gnd - l10 gnd - l11 gnd - l11 gnd - l12 gnd - l12 gnd - l13 gnd - l13 gnd - l15 gnd - l15 gnd - l8 gnd - l8 gnd - m10 gnd - m10 gnd - m11 gnd - m11 gnd - m12 gnd - m12 gnd - m13 gnd - m13 gnd - m15 gnd - m15 gnd - m8 gnd - m8 gnd - n10 gnd - n10 gnd - n11 gnd - n11 gnd - n12 gnd - n12 gnd - n13 gnd - n13 gnd - n15 gnd - n15 gnd - n8 gnd - n8 gnd - p14 gnd - p14 gnd - p20 gnd - p20 gnd - p3 gnd - p3 gnd - p9 gnd - p9 gnd - r10 gnd - r10 gnd - r11 gnd - r11 gnd - r12 gnd - r12 gnd - r13 gnd - r13 gnd - u17 gnd - u17 gnd - u6 gnd - u6 gnd - w 2 gnd - w 2 gnd - w 21 gnd - w 21 gnd - y14 gnd - y14 gnd - y9 gnd - y9 gnd - h6 nc - h6 pl25a 7 lum0_spllt_in_a t j6 nc - j6 pl25b 7 lum0_spllc_in_a c h3 nc - h3 pl26a 7 lum0_spllt_fb_a t h2 nc - h2 pl26b 7 lum0_spllc_fb_a c h17 nc - h17 pr26b 2 rum0_spllc_fb_a c h16 nc - h16 pr26a 2 rum0_spllt_fb_a t lfe2-35e/35se and lfe2-50e/50se logic signal connections: 484 fpbga (cont.) lfe2-35e/35se lfe2-50e/50se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-67 pinout information lattice semiconductor latticeecp2/m family data sheet h20 nc - h20 pr25b 2 rum0_spllc_in_a c h18 nc - h18 pr25a 2 rum0_spllt_in_a t * supports true lvds outputs. ** these dedicated input pins can be used for gplls or gdlls within the respective quadrant. lfe2-35e/35se and lfe2-50e/50se logic signal connections: 484 fpbga (cont.) lfe2-35e/35se lfe2-50e/50se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-68 pinout information lattice semiconductor latticeecp2/m family data sheet lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential d2 pl2a 7 vref2_7 t* d2 pl2a 7 vref2_7 t* d1 pl2b 7 vref1_7 c* d1 pl2b 7 vref1_7 c* gnd gndio7 7 gndio gndio7 7 f6 pl3a 7 t f6 pl3a 7 t f5 pl3b 7 c f5 pl3b 7 c vccio vccio7 7 vccio vccio7 7 e4 nc - e4 pl4a 7 t* e3 nc - e3 pl4b 7 c* e2 nc - e2 pl5a 7 t e1 nc - e1 pl5b 7 c gnd gndio7 7 gndio gndio7 7 h6 nc - h6 pl6a 7 ldqs6 t* h5 nc - h5 pl6b 7 c* f2 nc - f2 pl7a 7 t vccio vccio7 7 vccio vccio7 7 f1 nc - f1 pl7b 7 c h8 nc - h8 pl8a 7 t* j9 nc - j9 pl8b 7 c* g4 nc - g4 pl9a 7 t gnd gndio7 7 gndio gndio7 7 g3 nc - g3 pl9b 7 c h7 pl4a 7 t* h7 pl10a 7 t* j8 pl4b 7 c* j8 pl10b 7 c* g2 pl5a 7 t g2 pl11a 7 t g1 pl5b 7 c g1 pl11b 7 c h3 pl6a 7 t* h3 pl12a 7 t* vccio vccio7 7 vccio vccio7 7 h4 pl6b 7 c* h4 pl12b 7 c* j5 pl7a 7 t j5 pl13a 7 t j4 pl7b 7 c j4 pl13b 7 c j3 pl8a 7 ldqs8 t* j3 pl14a 7 ldqs14 t* gnd gndio7 7 gndio gndio7 7 k4 pl8b 7 c* k4 pl14b 7 c* h1 pl9a 7 t h1 pl15a 7 t h2 pl9b 7 c h2 pl15b 7 c vccio vccio7 7 vccio vccio7 7 k6 pl10a 7 t* k6 pl16a 7 t* k7 pl10b 7 c* k7 pl16b 7 c* j1 pl11a 7 t j1 pl17a 7 t j2 pl11b 7 c j2 pl17b 7 c gnd gndio7 7 gnd gndio7 7 vccio vccio7 7 vccio vccio7 7 k3 nc - k3 nc - k2 nc - k2 nc -
4-69 pinout information lattice semiconductor latticeecp2/m family data sheet gnd gndio7 7 gnd gndio7 7 k1 nc - k1 nc - l2 nc - l2 nc - l1 nc - l1 nc - vccio vccio7 7 vccio vccio7 7 m2 nc - m2 nc - m1 nc - m1 nc - n2 nc - n2 nc - gnd gndio7 7 gnd gndio7 7 m8 vcc - m8 nc - vccio vccio7 7 vccio vccio7 7 gnd gndio7 7 gnd gndio7 7 vccio vccio7 7 vccio vccio7 7 gnd gndio7 7 gnd gndio7 7 n1 pl12a 7 n1 pl18a 7 l8 pl13a 7 t l8 pl19a 7 t k8 pl13b 7 c k8 pl19b 7 c vccio vccio7 7 vccio vccio7 7 l6 pl14a 7 t* l6 pl20a 7 t* k5 pl14b 7 c* k5 pl20b 7 c* l7 pl15a 7 t l7 pl21a 7 t l5 pl15b 7 c l5 pl21b 7 c gnd gndio7 7 gnd gndio7 7 p1 pl16a 7 ldqs16 t* p1 pl22a 7 ldqs22 t* p2 pl16b 7 c* p2 pl22b 7 c* m6 pl17a 7 t m6 pl23a 7 t vccio vccio7 7 vccio vccio7 7 n8 pl17b 7 c n8 pl23b 7 c r1 pl18a 7 t* r1 pl24a 7 t* r2 pl18b 7 c* r2 pl24b 7 c* m7 pl19a 7 pclkt7_0 t m7 pl25a 7 pclkt7_0 t gnd gndio7 7 gnd gndio7 7 n9 pl19b 7 pclkc7_0 c n9 pl25b 7 pclkc7_0 c m4 pl21a 6 pclkt6_0 t* m4 pl27a 6 pclkt6_0 t* m5 pl21b 6 pclkc6_0 c* m5 pl27b 6 pclkc6_0 c* n7 pl22a 6 vref2_6 t n7 pl28a 6 vref2_6 t p9 pl22b 6 vref1_6 c p9 pl28b 6 vref1_6 c n3 pl23a 6 t* n3 pl29a 6 t* vccio vccio6 6 vccio vccio6 6 n4 pl23b 6 c* n4 pl29b 6 c* n5 pl24a 6 t n5 pl30a 6 t p7 pl24b 6 c p7 pl30b 6 c t1 nc - t1 pl31a 6 ldqs31 t* gnd gndio6 6 gndio gndio6 6 lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-70 pinout information lattice semiconductor latticeecp2/m family data sheet t2 nc - t2 pl31b 6 c* p8 nc - p8 pl32a 6 t p6 nc - p6 pl32b 6 c vccio vccio6 6 vccio vccio6 6 p5 nc - p5 pl33a 6 t* p4 nc - p4 pl33b 6 c* u1 nc - u1 pl34a 6 t v1 nc - v1 pl34b 6 c gnd gndio6 6 gndio gndio6 6 p3 nc - p3 nc - r3 nc - r3 nc - r4 nc - r4 nc - u2 nc - u2 nc - vccio vccio6 6 vccio vccio6 6 v2 nc - v2 nc - w 2nc- w 2nc- t6 nc - t6 pl38a 6 t r5 nc - r5 pl38b 6 c gnd gndio6 6 gnd gndio6 6 r6 pl25a 6 ldqs25 t* r6 pl39a 6 ldqs39 t* r7 pl25b 6 c* r7 pl39b 6 c* w 1 pl26a 6 t w 1 pl40a 6 t vccio vccio6 6 vccio vccio6 6 y2 pl26b 6 c y2 pl40b 6 c y1 pl27a 6 llm0_gdllt_in_a** t* y1 pl41a 6 llm0_gdllt_in_a** t* aa2 pl27b 6 llm0_gdllc_in_a** c* aa2 pl41b 6 llm0_gdllc_in_a** c* t5 pl28a 6 llm0_gdllt_fb_a t t5 pl42a 6 llm0_gdllt_fb_a t gnd gndio6 6 gnd gndio6 6 t7 pl28b 6 llm0_gdllc_fb_a c t7 pl42b 6 llm0_gdllc_fb_a c r8 vcc 6 r8 vccpll 6 t8 llm0_pllcap 6 t8 llm0_pllcap 6 u3 pl30a 6 llm0_gpllt_in_a** t* u3 pl44a 6 llm0_gpllt_in_a** t* u4 pl30b 6 llm0_gpllc_in_a** c* u4 pl44b 6 llm0_gpllc_in_a** c* v3 pl31a 6 llm0_gpllt_fb_a t v3 pl45a 6 llm0_gpllt_fb_a t u5 pl31b 6 llm0_gpllc_fb_a c u5 pl45b 6 llm0_gpllc_fb_a c v4 pl32a 6 t* v4 pl46a 6 t* vccio vccio6 6 vccio vccio6 6 v5 pl32b 6 c* v5 pl46b 6 c* y3 pl33a 6 t y3 pl47a 6 t y4 pl33b 6 c y4 pl47b 6 c w 3 pl34a 6 ldqs34 t* w 3 pl48a 6 ldqs48 t* gnd gndio6 6 gnd gndio6 6 w 4 pl34b 6 c* w 4 pl48b 6 c* aa1 pl35a 6 t aa1 pl49a 6 t lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-71 pinout information lattice semiconductor latticeecp2/m family data sheet ab1 pl35b 6 c ab1 pl49b 6 c vccio vccio6 6 vccio vccio6 6 u8 pl36a 6 t* u8 pl50a 6 t* u7 pl36b 6 c* u7 pl50b 6 c* v8 pl37a 6 t v8 pl51a 6 t u6 pl37b 6 c u6 pl51b 6 c gnd gndio6 6 gndio gndio6 6 w 6 pl38a 6 t* w 6 pl52a 6 t* w 5 pl38b 6 c* w 5 pl52b 6 c* ac1 pl39a 6 t ac1 pl53a 6 t ad1 pl39b 6 c ad1 pl53b 6 c vccio vccio6 6 vccio vccio6 6 y6 pl40a 6 t* y6 pl54a 6 t* y5 pl40b 6 c* y5 pl54b 6 c* ae2 pl41a 6 t ae2 pl55a 6 t ad2 pl41b 6 c ad2 pl55b 6 c gnd gndio6 6 gndio gndio6 6 ab3 pl42a 6 ldqs42 t* ab3 pl56a 6 ldqs56 t* ab2 pl42b 6 c* ab2 pl56b 6 c* w 7 pl43a 6 t w 7 pl57a 6 t vccio vccio6 6 vccio vccio6 6 w 8 pl43b 6 c w 8 pl57b 6 c y7 pl44a 6 t* y7 pl58a 6 t* y8 pl44b 6 c* y8 pl58b 6 c* ac2 pl45a 6 t ac2 pl59a 6 t gnd gndio6 6 gndio gndio6 6 ad3 pl45b 6 c ad3 pl59b 6 c ac3 tck - ac3 tck - aa8 tdi - aa8 tdi - ab4 tms - ab4 tms - aa5 tdo - aa5 tdo - ab5 vccj - ab5 vccj - ae3 pb2a 5 vref2_5 t ae3 pb2a 5 vref2_5 t af3 pb2b 5 vref1_5 c af3 pb2b 5 vref1_5 c ac4 pb3a 5 t ac4 pb3a 5 t ad4 pb3b 5 c ad4 pb3b 5 c ae4 pb4a 5 t ae4 pb4a 5 t af4 pb4b 5 c af4 pb4b 5 c vccio vccio5 5 vccio vccio5 5 v9 pb5a 5 t v9 pb5a 5 t w 9 pb5b 5 c w 9 pb5b 5 c gnd gndio5 5 gnd gndio5 5 aa6 pb6a 5 bdqs6 t aa6 pb6a 5 bdqs6 t ab6 pb6b 5 c ab6 pb6b 5 c lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-72 pinout information lattice semiconductor latticeecp2/m family data sheet ac5 pb7a 5 t ac5 pb7a 5 t ad5 pb7b 5 c ad5 pb7b 5 c aa7 pb8a 5 t aa7 pb8a 5 t ab7 pb8b 5 c ab7 pb8b 5 c vccio vccio5 5 vccio vccio5 5 ae5 pb9a 5 t ae5 pb9a 5 t af5 pb9b 5 c af5 pb9b 5 c ac7 pb10a 5 t ac7 pb10a 5 t ad7 pb10b 5 c ad7 pb10b 5 c gnd gndio5 5 gnd gndio5 5 vccio vccio5 5 vccio vccio5 5 gnd gndio5 5 gnd gndio5 5 vccio vccio5 5 vccio vccio5 5 gnd gndio5 5 gnd gndio5 5 w 10 pb11a 5 t w 10 pb11a 5 t y10 pb11b 5 c y10 pb11b 5 c w 11 pb12a 5 t w 11 pb12a 5 t aa10 pb12b 5 c aa10 pb12b 5 c ac8 pb13a 5 t ac8 pb13a 5 t ad8 pb13b 5 c ad8 pb13b 5 c vccio vccio5 5 vccio vccio5 5 ab8 pb14a 5 t ab8 pb14a 5 t ab10 pb14b 5 c ab10 pb14b 5 c gnd gndio5 5 gnd gndio5 5 ae6 pb15a 5 bdqs15 t ae6 pb15a 5 bdqs15 t af6 pb15b 5 c af6 pb15b 5 c aa11 pb16a 5 t aa11 pb16a 5 t ac9 pb16b 5 c ac9 pb16b 5 c ab9 pb17a 5 t ab9 pb17a 5 t ad9 pb17b 5 c ad9 pb17b 5 c vccio vccio5 5 vccio vccio5 5 y11 pb18a 5 t y11 pb18a 5 t ab11 pb18b 5 c ab11 pb18b 5 c ae7 pb19a 5 t ae7 pb19a 5 t af7 pb19b 5 c af7 pb19b 5 c gnd gndio5 5 gnd gndio5 5 ac10 pb20a 5 t ac10 pb20a 5 t ad10 pb20b 5 c ad10 pb20b 5 c aa12 pb21a 5 t aa12 pb21a 5 t w 12 pb21b 5 c w 12 pb21b 5 c ab12 pb22a 5 t ab12 pb22a 5 t vccio vccio5 5 vccio vccio5 5 y12 pb22b 5 c y12 pb22b 5 c ad12 pb23a 5 t ad12 pb23a 5 t lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-73 pinout information lattice semiconductor latticeecp2/m family data sheet ac12 pb23b 5 c ac12 pb23b 5 c ac13 pb24a 5 bdqs24 t ac13 pb24a 5 bdqs24 t gnd gndio5 5 gnd gndio5 5 aa13 pb24b 5 c aa13 pb24b 5 c ad13 pb25a 5 t ad13 pb25a 5 t ac14 pb25b 5 c ac14 pb25b 5 c ae8 pb26a 5 t ae8 pb26a 5 t vccio vccio5 5 vccio vccio5 5 af8 pb26b 5 c af8 pb26b 5 c ab15 pb27a 5 t ab15 pb27a 5 t y13 pb27b 5 c y13 pb27b 5 c ae9 pb28a 5 t ae9 pb28a 5 t gnd gndio5 5 gnd gndio5 5 af9 pb28b 5 c af9 pb28b 5 c w 13 pb29a 5 t w 13 pb29a 5 t aa14 pb29b 5 c aa14 pb29b 5 c ae10 pb30a 5 t ae10 pb30a 5 t af10 pb30b 5 c af10 pb30b 5 c w 14 pb31a 5 t w 14 pb31a 5 t ab13 pb31b 5 c ab13 pb31b 5 c vccio vccio5 5 vccio vccio5 5 y14 pb32a 5 t y14 pb32a 5 t ab14 pb32b 5 c ab14 pb32b 5 c gnd gndio5 5 gnd gndio5 5 ae11 pb33a 5 bdqs33 t ae11 pb33a 5 bdqs33 t af11 pb33b 5 c af11 pb33b 5 c ad14 pb34a 5 t ad14 pb34a 5 t aa15 pb34b 5 c aa15 pb34b 5 c ae12 pb35a 5 pclkt5_0 t ae12 pb35a 5 pclkt5_0 t af12 pb35b 5 pclkc5_0 c af12 pb35b 5 pclkc5_0 c vccio vccio5 5 vccio vccio5 5 gnd gndio5 5 gnd gndio5 5 ad15 pb40a 4 pclkt4_0 t ad15 pb40a 4 pclkt4_0 t vccio vccio4 4 vccio vccio4 4 ac15 pb40b 4 pclkc4_0 c ac15 pb40b 4 pclkc4_0 c ae13 pb41a 4 t ae13 pb41a 4 t af13 pb41b 4 c af13 pb41b 4 c ab17 pb42a 4 bdqs42 t ab17 pb42a 4 bdqs42 t gnd gndio4 4 gnd gndio4 4 y15 pb42b 4 c y15 pb42b 4 c ae14 pb43a 4 t ae14 pb43a 4 t af14 pb43b 4 c af14 pb43b 4 c aa16 pb44a 4 t aa16 pb44a 4 t vccio vccio4 4 vccio vccio4 4 lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-74 pinout information lattice semiconductor latticeecp2/m family data sheet w 15 pb44b 4 c w 15 pb44b 4 c ac17 pb45a 4 t ac17 pb45a 4 t ab16 pb45b 4 c ab16 pb45b 4 c ae15 pb46a 4 t ae15 pb46a 4 t gnd gndio4 4 gnd gndio4 4 af15 pb46b 4 c af15 pb46b 4 c ae16 pb47a 4 t ae16 pb47a 4 t af16 pb47b 4 c af16 pb47b 4 c y16 pb48a 4 t y16 pb48a 4 t ab18 pb48b 4 c ab18 pb48b 4 c ad17 pb49a 4 t ad17 pb49a 4 t ad18 pb49b 4 c ad18 pb49b 4 c vccio vccio4 4 vccio vccio4 4 ac18 pb50a 4 t ac18 pb50a 4 t ad19 pb50b 4 c ad19 pb50b 4 c gnd gndio4 4 gnd gndio4 4 ac19 pb51a 4 bdqs51 t ac19 pb51a 4 bdqs51 t ae17 pb51b 4 c ae17 pb51b 4 c ab19 pb52a 4 t ab19 pb52a 4 t ae19 pb52b 4 c ae19 pb52b 4 c af17 pb53a 4 t af17 pb53a 4 t ae18 pb53b 4 c ae18 pb53b 4 c vccio vccio4 4 vccio vccio4 4 w 16 pb54a 4 t w 16 pb54a 4 t aa17 pb54b 4 c aa17 pb54b 4 c af18 pb55a 4 t af18 pb55a 4 t af19 pb55b 4 c af19 pb55b 4 c gnd gndio4 4 gnd gndio4 4 aa19 nc - aa19 pb56a 4 t w 17 nc - w 17 pb56b 4 c y19 nc - y19 pb57a 4 t y17 nc - y17 pb57b 4 c af20 nc - af20 nc - vccio vccio4 4 vccio vccio4 4 ae20 nc - ae20 nc - aa20 nc - aa20 nc - w 18 nc - w 18 nc - ad20 nc - ad20 nc - gnd gndio4 4 gnd gndio4 4 ae21 nc - ae21 nc - af21 nc - af21 nc - af22 nc - af22 nc - vccio vccio4 4 vccio vccio4 4 gnd gndio4 4 gnd gndio4 4 lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-75 pinout information lattice semiconductor latticeecp2/m family data sheet ae22 pb56a 4 t ae22 pb65a 4 t ad22 pb56b 4 c ad22 pb65b 4 c af23 pb57a 4 t af23 pb66a 4 t ae23 pb57b 4 c ae23 pb66b 4 c ad23 pb58a 4 t ad23 pb67a 4 t ac23 pb58b 4 c ac23 pb67b 4 c vccio vccio4 4 vccio vccio4 4 ab20 pb59a 4 t ab20 pb68a 4 t ac20 pb59b 4 c ac20 pb68b 4 c gnd gndio4 4 gnd gndio4 4 ab21 pb60a 4 bdqs60 t ab21 pb69a 4 bdqs69 t ac22 pb60b 4 c ac22 pb69b 4 c w 19 pb61a 4 t w 19 pb70a 4 t aa21 pb61b 4 c aa21 pb70b 4 c af24 pb62a 4 t af24 pb71a 4 t ae24 pb62b 4 c ae24 pb71b 4 c vccio vccio4 4 vccio vccio4 4 y20 pb63a 4 t y20 pb72a 4 t ab22 pb63b 4 c ab22 pb72b 4 c y21 pb64a 4 vref2_4 t y21 pb73a 4 vref2_4 t ab23 pb64b 4 vref1_4 c ab23 pb73b 4 vref1_4 c gnd gndio4 4 gnd gndio4 4 ad24 cfg2 8 ad24 cfg2 8 w 20 cfg1 8 w 20 cfg1 8 ac24 cfg0 8 ac24 cfg0 8 v19 programn 8 v19 programn 8 aa22 cclk 8 aa22 cclk 8 ab24 initn 8 ab24 initn 8 ad25 done 8 ad25 done 8 gnd gndio8 8 gnd gndio 8 w 21 pr44b 8 w riten c w 21 pr58b 8 w riten c y22 pr44a 8 cs1n t y22 pr58a 8 cs1n t ac25 pr43b 8 csn c ac25 pr57b 8 csn c ab25 pr43a 8 d0 t ab25 pr57a 8 d0 t vccio vccio8 8 vccio vccio8 8 ad26 pr42b 8 d1 c ad26 pr56b 8 d1 c ac26 pr42a 8 d2 t ac26 pr56a 8 d2 t y23 pr41b 8 d3 c y23 pr55b 8 d3 c gnd gndio8 8 gnd gndio 8 w 22 pr41a 8 d4 t w 22 pr55a 8 d4 t aa25 pr40b 8 d5 c aa25 pr54b 8 d5 c ab26 pr40a 8 d6 t ab26 pr54a 8 d6 t w 23 pr39b 8 d7 c w 23 pr53b 8 d7 c vccio vccio8 8 vccio vccio8 8 lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-76 pinout information lattice semiconductor latticeecp2/m family data sheet v22 pr39a 8 di t v22 pr53a 8 di t y24 pr38b 8 dout,cson c y24 pr52b 8 dout_cson c y25 pr38a 8 busy t y25 pr52a 8 busy t w 24 pr37b 3 c w 24 pr51b 3 c gnd gndio3 3 gnd gndio3 3 v23 pr37a 3 t v23 pr51a 3 t aa26 pr36b 3 c* aa26 pr50b 3 c* y26 pr36a 3 t* y26 pr50a 3 t* u21 pr35b 3 c u21 pr49b 3 c vccio vccio3 3 vccio vccio3 3 u19 pr35a 3 t u19 pr49a 3 t w 25 pr34b 3 c* w 25 pr48b 3 c* w 26 pr34a 3 rdqs34 t* w 26 pr48a 3 rdqs48 t* gnd gndio3 3 gnd gndio3 3 v24 pr33b 3 c v24 pr47b 3 c v25 pr33a 3 t v25 pr47a 3 t v26 pr32b 3 c* v26 pr46b 3 c* u26 pr32a 3 t* u26 pr46a 3 t* vccio vccio3 3 vccio vccio3 3 u22 pr31b 3 rlm0_gpllc_fb_a c u22 pr45b 3 rlm0_gpllc_fb_a c u23 pr31a 3 rlm0_gpllt_fb_a t u23 pr45a 3 rlm0_gpllt_fb_a t u24 pr30b 3 rlm0_gpllc_in_a** c* u24 pr44b 3 rlm0_gpllc_in_a** c* u25 pr30a 3 rlm0_gpllt_in_a** t* u25 pr44a 3 rlm0_gpllt_in_a** t* r20 rlm0_pllcap 3 r20 rlm0_pllcap 3 p18 vcc 3 p18 vccpll 3 t19 pr28b 3 rlm0_gdllc_fb_a c t19 pr42b 3 rlm0_gdllc_fb_a c u20 pr28a 3 rlm0_gdllt_fb_a t u20 pr42a 3 rlm0_gdllt_fb_a t gnd gndio3 3 gnd gndio3 3 t25 pr27b 3 rlm0_gdllc_in_a** c* t25 pr41b 3 rlm0_gdllc_in_a** c* t26 pr27a 3 rlm0_gdllt_in_a** t* t26 pr41a 3 rlm0_gdllt_in_a** t* t20 pr26b 3 c t20 pr40b 3 c t22 pr26a 3 t t22 pr40a 3 t vccio vccio3 3 vccio vccio3 3 r26 pr25b 3 c* r26 pr39b 3 c* r25 pr25a 3 rdqs25 t* r25 pr39a 3 rdqs39 t* r22 nc - r22 pr38b 3 c gnd gndio3 3 gnd gndio3 3 t21 nc - t21 pr38a 3 t p26 nc - p26 nc - p25 nc - p25 nc - r24 nc - r24 nc - vccio vccio3 3 vccio vccio3 3 r23 nc - r23 nc - p20 nc - p20 nc - lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-77 pinout information lattice semiconductor latticeecp2/m family data sheet r19 nc - r19 nc - p21 nc - p21 pr34b 3 c gnd gndio3 3 gnd gndio3 3 p19 nc - p19 pr34a 3 t p23 nc - p23 pr33b 3 c* p22 nc - p22 pr33a 3 t* n22 nc - n22 pr32b 3 c vccio vccio3 3 vccio vccio3 3 r21 nc - r21 pr32a 3 t n26 nc - n26 pr31b 3 c* n25 nc - n25 pr31a 3 rdqs31 t* gnd gndio3 3 gnd gndio3 3 n19 pr24b 3 c n19 pr30b 3 c n20 pr24a 3 t n20 pr30a 3 t m26 pr23b 3 c* m26 pr29b 3 c* m25 pr23a 3 t* m25 pr29a 3 t* vccio vccio3 3 vccio vccio3 3 n18 pr22b 3 vref2_3 c n18 pr28b 3 vref2_3 c n21 pr22a 3 vref1_3 t n21 pr28a 3 vref1_3 t l26 pr21b 3 pclkc3_0 c* l26 pr27b 3 pclkc3_0 c* l25 pr21a 3 pclkt3_0 t* l25 pr27a 3 pclkt3_0 t* n24 pr19b 2 pclkc2_0 c n24 pr25b 2 pclkc2_0 c m23 pr19a 2 pclkt2_0 t m23 pr25a 2 pclkt2_0 t gnd gndio2 2 gnd gndio2 2 l21 pr18b 2 c* l21 pr24b 2 c* k22 pr18a 2 t* k22 pr24a 2 t* m24 pr17b 2 c m24 pr23b 2 c n23 pr17a 2 t n23 pr23a 2 t vccio vccio2 2 vccio vccio2 2 k26 pr16b 2 c* k26 pr22b 2 c* k25 pr16a 2 rdqs16 t* k25 pr22a 2 rdqs22 t* m20 pr15b 2 c m20 pr21b 2 c gnd gndio2 2 gnd gndio2 2 m19 pr15a 2 t m19 pr21a 2 t l22 pr14b 2 c* l22 pr20b 2 c* m22 pr14a 2 t* m22 pr20a 2 t* k21 pr13b 2 c k21 pr19b 2 c vccio vccio2 2 vccio vccio2 2 m21 pr13a 2 t m21 pr19a 2 t k24 pr12b 2 c* k24 pr18b 2 c* j24 pr12a 2 t* j24 pr18a 2 t* gnd gndio2 2 gnd gndio2 2 vccio vccio2 2 vccio vccio2 2 gnd gndio2 2 gnd gndio2 2 lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-78 pinout information lattice semiconductor latticeecp2/m family data sheet vccio vccio2 2 vccio vccio2 2 l20 vcc - l20 nc - gnd gndio2 2 gnd gndio2 2 j26 nc - j26 nc - j25 nc - j25 nc - j23 nc - j23 nc - k23 nc - k23 nc - vccio vccio2 2 vccio vccio2 2 h26 nc - h26 nc - h25 nc - h25 nc - h24 nc - h24 nc - gnd gndio2 2 gnd gndio2 2 h23 nc - h23 nc - vccio vccio2 2 vccio vccio2 2 g26 pr11b 2 c g26 pr17b 2 c gnd gndio2 2 gnd gndio2 2 g25 pr11a 2 t g25 pr17a 2 t f26 pr10b 2 c* f26 pr16b 2 c* f25 pr10a 2 t* f25 pr16a 2 t* k20 pr9b 2 c k20 pr15b 2 c vccio vccio2 2 vccio vccio2 2 l19 pr9a 2 t l19 pr15a 2 t e26 pr8b 2 c* e26 pr14b 2 c* e25 pr8a 2 rdqs8 t* e25 pr14a 2 rdqs14 t* gnd gndio2 2 gnd gndio2 2 j22 pr7b 2 c j22 pr13b 2 c h22 pr7a 2 t h22 pr13a 2 t g24 pr6b 2 c* g24 pr12b 2 c* g23 pr6a 2 t* g23 pr12a 2 t* vccio vccio2 2 vccio vccio2 2 k19 pr5b 2 c k19 pr11b 2 c j19 pr5a 2 t j19 pr11a 2 t d26 pr4b 2 c* d26 pr10b 2 c* c26 pr4a 2 t* c26 pr10a 2 t* f22 nc - f22 pr9b 2 c e24 nc - e24 pr9a 2 t gnd gndio2 2 gnd gndio2 2 d25 nc - d25 pr8b 2 c* c25 nc - c25 pr8a 2 t* d24 nc - d24 pr7b 2 c b25 nc - b25 pr7a 2 t vccio vccio2 2 vccio vccio2 2 h21 nc - h21 pr6b 2 c* g22 nc - g22 pr6a 2 rdqs6 t* lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-79 pinout information lattice semiconductor latticeecp2/m family data sheet b24 nc - b24 pr5b 2 c gnd gndio2 2 gnd gndio2 2 c24 nc - c24 pr5a 2 t d23 nc - d23 pr4b 2 c* c23 nc - c23 pr4a 2 t* g21 pr3b 2 c g21 pr3b 2 c vccio vccio2 2 vccio vccio2 2 h20 pr3a 2 t h20 pr3a 2 t gnd gndio2 2 gnd gndio2 2 e22 pr2b 2 vref2_2 c* e22 pr2b 2 vref2_2 c* f21 pr2a 2 vref1_2 t* f21 pr2a 2 vref1_2 t* e23 pt64b 1 vref2_1 c e23 pt73b 1 vref2_1 c gnd gndio1 1 gnd gndio1 1 d22 pt64a 1 vref1_1 t d22 pt73a 1 vref1_1 t g20 pt63b 1 c g20 pt72b 1 c j18 pt63a 1 t j18 pt72a 1 t f20 pt62b 1 c f20 pt71b 1 c vccio vccio1 1 vccio vccio1 1 h19 pt62a 1 t h19 pt71a 1 t a24 pt61b 1 c a24 pt70b 1 c a23 pt61a 1 t a23 pt70a 1 t e21 pt60b 1 c e21 pt69b 1 c f19 pt60a 1 t f19 pt69a 1 t c22 pt59b 1 c c22 pt68b 1 c gnd gndio1 1 gnd gndio1 1 e20 pt59a 1 t e20 pt68a 1 t b22 pt58b 1 c b22 pt67b 1 c vccio vccio1 1 vccio vccio1 1 b23 pt58a 1 t b23 pt67a 1 t c20 pt57b 1 c c20 pt66b 1 c d20 pt57a 1 t d20 pt66a 1 t a22 pt56b 1 c a22 pt65b 1 c a21 pt56a 1 t a21 pt65a 1 t gnd gndio1 1 gnd gndio1 1 e19 nc - e19 nc - c19 nc - c19 nc - vccio vccio1 1 vccio vccio1 1 b21 nc - b21 nc - b20 nc - b20 nc - d19 nc - d19 nc - b19 nc - b19 nc - gnd gndio1 1 gnd gndio1 1 g17 nc - g17 nc - e18 nc - e18 nc - lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-80 pinout information lattice semiconductor latticeecp2/m family data sheet g19 nc - g19 nc - f17 nc - f17 nc - vccio vccio1 1 vccio vccio1 1 a20 nc - a20 nc - a19 nc - a19 nc - e17 nc - e17 nc - d18 nc - d18 nc - b18 pt55b 1 c b18 pt55b 1 c gnd gndio1 1 gnd gndio1 1 a18 pt55a 1 t a18 pt55a 1 t e16 pt54b 1 c e16 pt54b 1 c g16 pt54a 1 t g16 pt54a 1 t f16 pt53b 1 c f16 pt53b 1 c vccio vccio1 1 vccio vccio1 1 h18 pt53a 1 t h18 pt53a 1 t a17 pt52b 1 c a17 pt52b 1 c b17 pt52a 1 t b17 pt52a 1 t c18 pt51b 1 c c18 pt51b 1 c b16 pt51a 1 t b16 pt51a 1 t c17 pt50b 1 c c17 pt50b 1 c gnd gndio1 1 gnd gndio1 1 d17 pt50a 1 t d17 pt50a 1 t e15 pt49b 1 c e15 pt49b 1 c vccio vccio1 1 vccio vccio1 1 g15 pt49a 1 t g15 pt49a 1 t a16 pt48b 1 c a16 pt48b 1 c b15 pt48a 1 t b15 pt48a 1 t d15 pt47b 1 c d15 pt47b 1 c f15 pt47a 1 t f15 pt47a 1 t a14 pt46b 1 c a14 pt46b 1 c b14 pt46a 1 t b14 pt46a 1 t gnd gndio1 1 gnd gndio1 1 c15 pt45b 1 c c15 pt45b 1 c a15 pt45a 1 t a15 pt45a 1 t a13 pt44b 1 c a13 pt44b 1 c b13 pt44a 1 t b13 pt44a 1 t vccio vccio1 1 vccio vccio1 1 h17 pt43b 1 c h17 pt43b 1 c h15 pt43a 1 t h15 pt43a 1 t d13 pt42b 1 c d13 pt42b 1 c c14 pt42a 1 t c14 pt42a 1 t gnd gndio1 1 gnd gndio1 1 g14 pt41b 1 c g14 pt41b 1 c e14 pt41a 1 t e14 pt41a 1 t lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-81 pinout information lattice semiconductor latticeecp2/m family data sheet a12 pt40b 1 c a12 pt40b 1 c b12 pt40a 1 t b12 pt40a 1 t vccio vccio1 1 vccio vccio1 1 f14 pt39b 1 pclkc1_0 c f14 pt39b 1 pclkc1_0 c d14 pt39a 1 pclkt1_0 t d14 pt39a 1 pclkt1_0 t h16 xres 1 h16 xres 1 h14 pt37b 0 pclkc0_0 c h14 pt37b 0 pclkc0_0 c gnd gndio0 0 gnd gndio0 0 h13 pt37a 0 pclkt0_0 t h13 pt37a 0 pclkt0_0 t a11 pt36b 0 c a11 pt36b 0 c b11 pt36a 0 t b11 pt36a 0 t c13 pt35b 0 c c13 pt35b 0 c vccio vccio0 0 vccio vccio0 0 e13 pt35a 0 t e13 pt35a 0 t d12 pt34b 0 c d12 pt34b 0 c f13 pt34a 0 t f13 pt34a 0 t a10 pt33b 0 c a10 pt33b 0 c b10 pt33a 0 t b10 pt33a 0 t c12 pt32b 0 c c12 pt32b 0 c gnd gndio0 0 gnd gndio0 0 c10 pt32a 0 t c10 pt32a 0 t g13 pt31b 0 c g13 pt31b 0 c vccio vccio0 0 vccio vccio0 0 h12 pt31a 0 t h12 pt31a 0 t a9 pt30b 0 c a9 pt30b 0 c b9 pt30a 0 t b9 pt30a 0 t e12 pt29b 0 c e12 pt29b 0 c g12 pt29a 0 t g12 pt29a 0 t a8 pt28b 0 c a8 pt28b 0 c b8 pt28a 0 t b8 pt28a 0 t gnd gndio0 0 gnd gndio0 0 e11 pt27b 0 c e11 pt27b 0 c c9 pt27a 0 t c9 pt27a 0 t a7 pt26b 0 c a7 pt26b 0 c b7 pt26a 0 t b7 pt26a 0 t vccio vccio0 0 vccio vccio0 0 f12 pt25b 0 c f12 pt25b 0 c d10 pt25a 0 t d10 pt25a 0 t h11 pt24b 0 c h11 pt24b 0 c g11 pt24a 0 t g11 pt24a 0 t gnd gndio0 0 gnd gndio0 0 a6 pt23b 0 c a6 pt23b 0 c b6 pt23a 0 t b6 pt23a 0 t d8 pt22b 0 c d8 pt22b 0 c lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-82 pinout information lattice semiconductor latticeecp2/m family data sheet c8 pt22a 0 t c8 pt22a 0 t vccio vccio0 0 vccio vccio0 0 f11 pt21b 0 c f11 pt21b 0 c e10 pt21a 0 t e10 pt21a 0 t e9 pt20b 0 c e9 pt20b 0 c d9 pt20a 0 t d9 pt20a 0 t g10 pt19b 0 c g10 pt19b 0 c gnd gndio0 0 gnd gndio0 0 h10 pt19a 0 t h10 pt19a 0 t a5 pt18b 0 c a5 pt18b 0 c b5 pt18a 0 t b5 pt18a 0 t c7 pt17b 0 c c7 pt17b 0 c vccio vccio0 0 vccio vccio0 0 d7 pt17a 0 t d7 pt17a 0 t e8 pt16b 0 c e8 pt16b 0 c f10 pt16a 0 t f10 pt16a 0 t f8 pt15b 0 c f8 pt15b 0 c h9 pt15a 0 t h9 pt15a 0 t c5 pt14b 0 c c5 pt14b 0 c gnd gndio0 0 gnd gndio0 0 d5 pt14a 0 t d5 pt14a 0 t b4 pt13b 0 b4 pt13b 0 vccio vccio0 0 vccio vccio0 0 gnd gndio0 0 gnd gndio0 0 vccio vccio0 0 vccio vccio0 0 gnd gndio0 0 gnd gndio0 0 vccio vccio0 0 vccio vccio0 0 c4 pt10b 0 c c4 pt10b 0 c gnd gndio0 0 gnd gndio0 0 c3 pt10a 0 t c3 pt10a 0 t a4 pt9b 0 c a4 pt9b 0 c a3 pt9a 0 t a3 pt9a 0 t b3 pt8b 0 c b3 pt8b 0 c vccio vccio0 0 vccio vccio0 0 b2 pt8a 0 t b2 pt8a 0 t d4 pt7b 0 c d4 pt7b 0 c d3 pt7a 0 t d3 pt7a 0 t c2 pt6b 0 c c2 pt6b 0 c c1 pt6a 0 t c1 pt6a 0 t g8 pt5b 0 c g8 pt5b 0 c gnd gndio0 0 gnd gndio0 0 g7 pt5a 0 t g7 pt5a 0 t e7 pt4b 0 c e7 pt4b 0 c vccio vccio0 0 vccio vccio0 0 lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-83 pinout information lattice semiconductor latticeecp2/m family data sheet f7 pt4a 0 t f7 pt4a 0 t e6 pt3b 0 c e6 pt3b 0 c e5 pt3a 0 t e5 pt3a 0 t g6 pt2b 0 vref2_0 c g6 pt2b 0 vref2_0 c g5 pt2a 0 vref1_0 t g5 pt2a 0 vref1_0 t l12 vcc - l12 vcc - l13 vcc - l13 vcc - l14 vcc - l14 vcc - l15 vcc - l15 vcc - m11 vcc - m11 vcc - m12 vcc - m12 vcc - m15 vcc - m15 vcc - m16 vcc - m16 vcc - n11 vcc - n11 vcc - n16 vcc - n16 vcc - p11 vcc - p11 vcc - p16 vcc - p16 vcc - r11 vcc - r11 vcc - r12 vcc - r12 vcc - r15 vcc - r15 vcc - r16 vcc - r16 vcc - t12 vcc - t12 vcc - t13 vcc - t13 vcc - t14 vcc - t14 vcc - t15 vcc - t15 vcc - d11 vccio0 0 d11 vccio0 0 d6 vccio0 0 d6 vccio0 0 g9 vccio0 0 g9 vccio0 0 k12 vccio0 0 k12 vccio0 0 j12 vccio0 0 j12 vccio0 0 d16 vccio1 1 d16 vccio1 1 d21 vccio1 1 d21 vccio1 1 g18 vccio1 1 g18 vccio1 1 j15 vccio1 1 j15 vccio1 1 k15 vccio1 1 k15 vccio1 1 f23 vccio2 2 f23 vccio2 2 j20 vccio2 2 j20 vccio2 2 l23 vccio2 2 l23 vccio2 2 m17 vccio2 2 m17 vccio2 2 m18 vccio2 2 m18 vccio2 2 aa23 vccio3 3 aa23 vccio3 3 r17 vccio3 3 r17 vccio3 3 r18 vccio3 3 r18 vccio3 3 t23 vccio3 3 t23 vccio3 3 lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-84 pinout information lattice semiconductor latticeecp2/m family data sheet v20 vccio3 3 v20 vccio3 3 ac16 vccio4 4 ac16 vccio4 4 ac21 vccio4 4 ac21 vccio4 4 u15 vccio4 4 u15 vccio4 4 v15 vccio4 4 v15 vccio4 4 y18 vccio4 4 y18 vccio4 4 ac11 vccio5 5 ac11 vccio5 5 ac6 vccio5 5 ac6 vccio5 5 u12 vccio5 5 u12 vccio5 5 v12 vccio5 5 v12 vccio5 5 y9 vccio5 5 y9 vccio5 5 aa4 vccio6 6 aa4 vccio6 6 r10 vccio6 6 r10 vccio6 6 r9 vccio6 6 r9 vccio6 6 t4 vccio6 6 t4 vccio6 6 v7 vccio6 6 v7 vccio6 6 f4 vccio7 7 f4 vccio7 7 j7 vccio7 7 j7 vccio7 7 l4 vccio7 7 l4 vccio7 7 m10 vccio7 7 m10 vccio7 7 m9 vccio7 7 m9 vccio7 7 ae25 vccio8 8 ae25 vccio8 8 v18 vccio8 8 v18 vccio8 8 j10 vccaux - j10 vccaux - j11 vccaux - j11 vccaux - j16 vccaux - j16 vccaux - j17 vccaux - j17 vccaux - k18 vccaux - k18 vccaux - k9 vccaux - k9 vccaux - l18 vccaux - l18 vccaux - l9 vccaux - l9 vccaux - t18 vccaux - t18 vccaux - t9 vccaux - t9 vccaux - u18 vccaux - u18 vccaux - u9 vccaux - u9 vccaux - v10 vccaux - v10 vccaux - v11 vccaux - v11 vccaux - v16 vccaux - v16 vccaux - v17 vccaux - v17 vccaux - a2 gnd - a2 gnd - a25 gnd - a25 gnd - aa18 gnd - aa18 gnd - aa24 gnd - aa24 gnd - aa3 gnd - aa3 gnd - lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-85 pinout information lattice semiconductor latticeecp2/m family data sheet aa9 gnd - aa9 gnd - ad11 gnd - ad11 gnd - ad16 gnd - ad16 gnd - ad21 gnd - ad21 gnd - ad6 gnd - ad6 gnd - ae1 gnd - ae1 gnd - ae26 gnd - ae26 gnd - af2 gnd - af2 gnd - af25 gnd - af25 gnd - b1 gnd - b1 gnd - b26 gnd - b26 gnd - c11 gnd - c11 gnd - c16 gnd - c16 gnd - c21 gnd - c21 gnd - c6 gnd - c6 gnd - f18 gnd - f18 gnd - f24 gnd - f24 gnd - f3 gnd - f3 gnd - f9 gnd - f9 gnd - j13 gnd - j13 gnd - j14 gnd - j14 gnd - j21 gnd - j21 gnd - j6 gnd - j6 gnd - k10 gnd - k10 gnd - k11 gnd - k11 gnd - k13 gnd - k13 gnd - k14 gnd - k14 gnd - k16 gnd - k16 gnd - k17 gnd - k17 gnd - l10 gnd - l10 gnd - l11 gnd - l11 gnd - l16 gnd - l16 gnd - l17 gnd - l17 gnd - l24 gnd - l24 gnd - l3 gnd - l3 gnd - m13 gnd - m13 gnd - m14 gnd - m14 gnd - n10 gnd - n10 gnd - n12 gnd - n12 gnd - n13 gnd - n13 gnd - n14 gnd - n14 gnd - n15 gnd - n15 gnd - n17 gnd - n17 gnd - p10 gnd - p10 gnd - lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-86 pinout information lattice semiconductor latticeecp2/m family data sheet p12 gnd - p12 gnd - p13 gnd - p13 gnd - p14 gnd - p14 gnd - p15 gnd - p15 gnd - p17 gnd - p17 gnd - r13 gnd - r13 gnd - r14 gnd - r14 gnd - t10 gnd - t10 gnd - t11 gnd - t11 gnd - t16 gnd - t16 gnd - t17 gnd - t17 gnd - t24 gnd - t24 gnd - t3 gnd - t3 gnd - u10 gnd - u10 gnd - u11 gnd - u11 gnd - u13 gnd - u13 gnd - u14 gnd - u14 gnd - u16 gnd - u16 gnd - u17 gnd - u17 gnd - v13 gnd - v13 gnd - v14 gnd - v14 gnd - v21 gnd - v21 gnd - v6 gnd - v6 gnd - m3 nc - m3 nc - n6 nc - n6 nc - p24 nc - p24 nc - *supports true lvds outputs. ** these dedicated input pins can be used for gplls or gdlls within the respective quadrant. lfe2-20e/20se and lfe2-35e/35se logic signal connections: 672 fpbga (cont.) lfe2-20e/20se lfe2-35e/35se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-87 pinout information lattice semiconductor latticeecp2/m family data sheet lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential d2 pl2a 7 vref2_7 t (lvds)* d2 pl2a 7 vref2_7 t (lvds)* d1 pl2b 7 vref1_7 c (lvds)* d1 pl2b 7 vref1_7 c (lvds)* gnd gndio7 7 gnd gndio7 7 f6 pl5a 7 t f6 pl18a 7 t f5 pl5b 7 c f5 pl18b 7 c vccio vccio7 7 vccio vccio7 7 e4 pl6a 7 t (lvds)* e4 pl19a 7 t (lvds)* e3 pl6b 7 c (lvds)* e3 pl19b 7 c (lvds)* e2 pl7a 7 t e2 pl20a 7 t e1 pl7b 7 c e1 pl20b 7 c gnd gndio7 7 gnd gndio7 7 h6 pl8a 7 ldqs8 t (lvds)* h6 pl21a 7 ldqs21 t (lvds)* h5 pl8b 7 c (lvds)* h5 pl21b 7 c (lvds)* f2 pl9a 7 t f2 pl22a 7 t vccio vccio7 7 vccio vccio7 7 f1 pl9b 7 c f1 pl22b 7 c h8 pl10a 7 t (lvds)* h8 pl23a 7 t (lvds)* j9 pl10b 7 c (lvds)* j9 pl23b 7 c (lvds)* g4 pl11a 7 t g4 pl24a 7 t gnd gndio7 7 gnd gndio7 7 g3 pl11b 7 c g3 pl24b 7 c h7 pl12a 7 t (lvds)* h7 pl25a 7 t (lvds)* j8 pl12b 7 c (lvds)* j8 pl25b 7 c (lvds)* g2 pl13a 7 t g2 pl26a 7 t g1 pl13b 7 c g1 pl26b 7 c h3 pl14a 7 t (lvds)* h3 pl27a 7 t (lvds)* vccio vccio7 7 vccio vccio7 7 h4 pl14b 7 c (lvds)* h4 pl27b 7 c (lvds)* j5 pl15a 7 t j5 pl28a 7 t j4 pl15b 7 c j4 pl28b 7 c j3 pl16a 7 ldqs16 t (lvds)* j3 pl29a 7 ldqs29 t (lvds)* gnd gndio7 7 gnd gndio7 7 k4 pl16b 7 c (lvds)* k4 pl29b 7 c (lvds)* h1 pl17a 7 t h1 pl30a 7 t h2 pl17b 7 c h2 pl30b 7 c vccio vccio7 7 vccio vccio7 7 k6 pl18a 7 t (lvds)* k6 pl31a 7 t (lvds)* k7 pl18b 7 c (lvds)* k7 pl31b 7 c (lvds)* j1 pl19a 7 t j1 pl32a 7 t j2 pl19b 7 c j2 pl32b 7 c gnd gndio7 7 gnd gndio7 7 vccio vccio7 7 vccio vccio7 7 k3 pl23a 7 t k3 pl36a 7 t k2 pl23b 7 c k2 pl36b 7 c
4-88 pinout information lattice semiconductor latticeecp2/m family data sheet gnd gndio7 7 gnd gndio7 7 k1 pl24a 7 t (lvds)* k1 pl37a 7 t (lvds)* l2 pl24b 7 c (lvds)* l2 pl37b 7 c (lvds)* l1 pl25a 7 lum0_spllt_in_a t l1 pl38a 7 lum0_spllt_in_a t vccio vccio7 7 vccio vccio7 7 m2 pl25b 7 lum0_spllc_in_a c m2 pl38b 7 lum0_spllc_in_a c m1 pl26a 7 lum0_spllt_fb_a t m1 pl39a 7 lum0_spllt_fb_a t n2 pl26b 7 lum0_spllc_fb_a c n2 pl39b 7 lum0_spllc_fb_a c gnd gndio7 7 gnd gndio7 7 m8 vccpll 7 m8 nc - vccio vccio7 7 vccio vccio7 7 gnd gndio7 7 gnd gndio7 7 vccio vccio7 7 vccio vccio7 7 gnd gndio7 7 gnd gndio7 7 n1 pl37a 7 n1 pl50a 7 l8 pl38a 7 t l8 pl51a 7 t k8 pl38b 7 c k8 pl51b 7 c vccio vccio7 7 vccio vccio7 7 l6 pl39a 7 t (lvds)* l6 pl52a 7 t (lvds)* k5 pl39b 7 c (lvds)* k5 pl52b 7 c (lvds)* l7 pl40a 7 t l7 pl53a 7 t l5 pl40b 7 c l5 pl53b 7 c gnd gndio7 7 gnd gndio7 7 p1 pl41a 7 ldqs41 t (lvds)* p1 pl54a 7 ldqs54 t (lvds)* p2 pl41b 7 c (lvds)* p2 pl54b 7 c (lvds)* m6 pl42a 7 t m6 pl55a 7 t vccio vccio7 7 vccio vccio7 7 n8 pl42b 7 c n8 pl55b 7 c r1 pl43a 7 t (lvds)* r1 pl56a 7 t (lvds)* r2 pl43b 7 c (lvds)* r2 pl56b 7 c (lvds)* m7 pl44a 7 pclkt7_0 t m7 pl57a 7 pclkt7_0 t gnd gndio7 7 gnd gndio7 7 n9 pl44b 7 pclkc7_0 c n9 pl57b 7 pclkc7_0 c m4 pl46a 6 pclkt6_0 t (lvds)* m4 pl59a 6 pclkt6_0 t (lvds)* m5 pl46b 6 pclkc6_0 c (lvds)* m5 pl59b 6 pclkc6_0 c (lvds)* n7 pl47a 6 vref2_6 t n7 pl60a 6 vref2_6 t p9 pl47b 6 vref1_6 c p9 pl60b 6 vref1_6 c n3 pl48a 6 t (lvds)* n3 pl61a 6 t (lvds)* vccio vccio6 6 vccio vccio6 6 n4 pl48b 6 c (lvds)* n4 pl61b 6 c (lvds)* n5 pl49a 6 t n5 pl62a 6 t p7 pl49b 6 c p7 pl62b 6 c t1 pl50a 6 ldqs50 t (lvds)* t1 pl63a 6 ldqs63 t (lvds)* gnd gndio6 6 gnd gndio6 6 lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-89 pinout information lattice semiconductor latticeecp2/m family data sheet t2 pl50b 6 c (lvds)* t2 pl63b 6 c (lvds)* p8 pl51a 6 t p8 pl64a 6 t p6 pl51b 6 c p6 pl64b 6 c vccio vccio6 6 vccio vccio6 6 p5 pl52a 6 t (lvds)* p5 pl65a 6 t (lvds)* p4 pl52b 6 c (lvds)* p4 pl65b 6 c (lvds)* u1 pl53a 6 t u1 pl66a 6 t v1 pl53b 6 c v1 pl66b 6 c gnd gndio6 6 gnd gndio6 6 p3 pl54a 6 t (lvds)* p3 pl67a 6 t (lvds)* r3 pl54b 6 c (lvds)* r3 pl67b 6 c (lvds)* r4 pl55a 6 t r4 pl68a 6 t u2 pl55b 6 c u2 pl68b 6 c vccio vccio6 6 vccio vccio6 6 v2 pl56a 6 t (lvds)* v2 pl69a 6 t (lvds)* w 2 pl56b 6 c (lvds)* w 2 pl69b 6 c (lvds)* t6 pl57a 6 t t6 pl70a 6 t r5 pl57b 6 c r5 pl70b 6 c gnd gndio6 6 gnd gndio6 6 r6 pl58a 6 ldqs58 t (lvds)* r6 pl71a 6 ldqs71 t (lvds)* r7 pl58b 6 c (lvds)* r7 pl71b 6 c (lvds)* w 1 pl59a 6 t w 1 pl72a 6 t vccio vccio6 6 vccio vccio6 6 y2 pl59b 6 c y2 pl72b 6 c y1 pl60a 6 llm0_gdllt_in_a** t (lvds)* y1 pl73a 6 llm0_gdllt_in_a** t (lvds)* aa2 pl60b 6 llm0_gdllc_in_a** c (lvds)* aa2 pl73b 6 llm0_gdllc_in_a** c (lvds)* t5 pl61a 6 llm0_gdllt_fb_a t t5 pl74a 6 llm0_gdllt_fb_a t gnd gndio6 6 gnd gndio6 6 t7 pl61b 6 llm0_gdllc_fb_d c t7 pl74b 6 llm0_gdllc_fb_d c r8 vccpll 6 r8 vccpll - t8 llm0_pllcap 6 t8 llm0_pllcap 6 u3 pl63a 6 llm0_gpllt_in_a** t (lvds)* u3 pl76a 6 llm0_gpllt_in_a** t (lvds)* u4 pl63b 6 llm0_gpllc_in_a** c (lvds)* u4 pl76b 6 llm0_gpllc_in_a** c (lvds)* v3 pl64a 6 llm0_gpllt_fb_a t v3 pl77a 6 llm0_gpllt_fb_a t u5 pl64b 6 llm0_gpllc_fb_a c u5 pl77b 6 llm0_gpllc_fb_a c v4 pl65a 6 t (lvds)* v4 pl78a 6 t (lvds)* vccio vccio6 6 vccio vccio6 6 v5 pl65b 6 c (lvds)* v5 pl78b 6 c (lvds)* y3 pl66a 6 t y3 pl79a 6 t y4 pl66b 6 c y4 pl79b 6 c w 3 pl67a 6 ldqs67 t (lvds)* w 3 pl80a 6 ldqs80 t (lvds)* gnd gndio6 6 gnd gndio6 6 w 4 pl67b 6 c (lvds)* w 4 pl80b 6 c (lvds)* aa1 pl68a 6 t aa1 pl81a 6 t lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-90 pinout information lattice semiconductor latticeecp2/m family data sheet ab1 pl68b 6 c ab1 pl81b 6 c vccio vccio6 6 vccio vccio6 6 u8 pl69a 6 t (lvds)* u8 pl82a 6 t (lvds)* u7 pl69b 6 c (lvds)* u7 pl82b 6 c (lvds)* v8 pl70a 6 t v8 pl83a 6 t u6 pl70b 6 c u6 pl83b 6 c gnd gndio6 6 gnd gndio6 6 w 6 pl71a 6 t (lvds)* w 6 pl84a 6 t (lvds)* w 5 pl71b 6 c (lvds)* w 5 pl84b 6 c (lvds)* ac1 pl72a 6 t ac1 pl85a 6 t ad1 pl72b 6 c ad1 pl85b 6 c vccio vccio6 6 vccio vccio6 6 y6 pl73a 6 t (lvds)* y6 pl86a 6 t (lvds)* y5 pl73b 6 c (lvds)* y5 pl86b 6 c (lvds)* ae2 pl74a 6 t ae2 pl87a 6 t ad2 pl74b 6 c ad2 pl87b 6 c gnd gndio6 6 gnd gndio6 6 ab3 pl75a 6 ldqs75 t (lvds)* ab3 pl88a 6 ldqs88 t (lvds)* ab2 pl75b 6 c (lvds)* ab2 pl88b 6 c (lvds)* w 7 pl76a 6 t w 7 pl89a 6 t vccio vccio6 6 vccio vccio6 6 w 8 pl76b 6 c w 8 pl89b 6 c y7 pl77a 6 t (lvds)* y7 pl90a 6 t (lvds)* y8 pl77b 6 c (lvds)* y8 pl90b 6 c (lvds)* ac2 pl78a 6 t ac2 pl91a 6 t gnd gndio6 6 gnd gndio6 6 ad3 pl78b 6 c ad3 pl91b 6 c ac3 tck - ac3 tck - aa8 tdi - aa8 tdi - ab4 tms - ab4 tms - aa5 tdo - aa5 tdo - ab5 vccj - ab5 vccj - ae3 pb2a 5 vref2_5 t ae3 pb2a 5 vref2_5 t af3 pb2b 5 vref1_5 c af3 pb2b 5 vref1_5 c ac4 pb3a 5 t ac4 pb3a 5 t ad4 pb3b 5 c ad4 pb3b 5 c ae4 pb4a 5 t ae4 pb4a 5 t af4 pb4b 5 c af4 pb4b 5 c vccio vccio5 5 vccio vccio5 5 v9 pb5a 5 t v9 pb5a 5 t w 9 pb5b 5 c w 9 pb5b 5 c gnd gndio5 5 gnd gndio5 5 aa6 pb6a 5 bdqs6 t aa6 pb6a 5 bdqs6 t ab6 pb6b 5 c ab6 pb6b 5 c lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-91 pinout information lattice semiconductor latticeecp2/m family data sheet ac5 pb7a 5 t ac5 pb7a 5 t ad5 pb7b 5 c ad5 pb7b 5 c aa7 pb8a 5 t aa7 pb8a 5 t ab7 pb8b 5 c ab7 pb8b 5 c vccio vccio5 5 vccio vccio5 5 ae5 pb9a 5 t ae5 pb9a 5 t af5 pb9b 5 c af5 pb9b 5 c ac7 pb10a 5 t ac7 pb10a 5 t ad7 pb10b 5 c ad7 pb10b 5 c gnd gndio5 5 gnd gndio5 5 vccio vccio5 5 vccio vccio5 5 gnd gndio5 5 gnd gndio5 5 vccio vccio5 5 vccio vccio5 5 gnd gndio5 5 gnd gndio5 5 w 10 pb20a 5 t w 10 pb29a 5 t y10 pb20b 5 c y10 pb29b 5 c w 11 pb21a 5 t w 11 pb30a 5 t aa10 pb21b 5 c aa10 pb30b 5 c ac8 pb22a 5 t ac8 pb31a 5 t ad8 pb22b 5 c ad8 pb31b 5 c vccio vccio5 5 vccio vccio5 5 ab8 pb23a 5 t ab8 pb32a 5 t ab10 pb23b 5 c ab10 pb32b 5 c gnd gndio5 5 gnd gndio5 5 ae6 pb24a 5 bdqs24 t ae6 pb33a 5 bdqs33 t af6 pb24b 5 c af6 pb33b 5 c aa11 pb25a 5 t aa11 pb34a 5 t ac9 pb25b 5 c ac9 pb34b 5 c ab9 pb26a 5 t ab9 pb35a 5 t ad9 pb26b 5 c ad9 pb35b 5 c vccio vccio5 5 vccio vccio5 5 y11 pb27a 5 t y11 pb36a 5 t ab11 pb27b 5 c ab11 pb36b 5 c ae7 pb28a 5 t ae7 pb37a 5 t af7 pb28b 5 c af7 pb37b 5 c gnd gndio5 5 gnd gndio5 5 ac10 pb29a 5 t ac10 pb38a 5 t ad10 pb29b 5 c ad10 pb38b 5 c aa12 pb30a 5 t aa12 pb39a 5 t w 12 pb30b 5 c w 12 pb39b 5 c ab12 pb31a 5 t ab12 pb40a 5 t vccio vccio5 5 vccio vccio5 5 y12 pb31b 5 c y12 pb40b 5 c ad12 pb32a 5 t ad12 pb41a 5 t lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-92 pinout information lattice semiconductor latticeecp2/m family data sheet ac12 pb32b 5 c ac12 pb41b 5 c ac13 pb33a 5 bdqs33 t ac13 pb42a 5 bdqs42 t gnd gndio5 5 gnd gndio5 5 aa13 pb33b 5 c aa13 pb42b 5 c ad13 pb34a 5 t ad13 pb43a 5 t ac14 pb34b 5 c ac14 pb43b 5 c ae8 pb35a 5 t ae8 pb44a 5 t vccio vccio5 5 vccio vccio5 5 af8 pb35b 5 c af8 pb44b 5 c ab15 pb36a 5 t ab15 pb45a 5 t y13 pb36b 5 c y13 pb45b 5 c ae9 pb37a 5 t ae9 pb46a 5 t gnd gndio5 5 gnd gndio5 5 af9 pb37b 5 c af9 pb46b 5 c w 13 pb38a 5 t w 13 pb47a 5 t aa14 pb38b 5 c aa14 pb47b 5 c ae10 pb39a 5 t ae10 pb48a 5 t af10 pb39b 5 c af10 pb48b 5 c w 14 pb40a 5 t w 14 pb49a 5 t ab13 pb40b 5 c ab13 pb49b 5 c vccio vccio5 5 vccio vccio5 5 y14 pb41a 5 t y14 pb50a 5 t ab14 pb41b 5 c ab14 pb50b 5 c gnd gndio5 5 gnd gndio5 5 ae11 pb42a 5 bdqs42 t ae11 pb51a 5 bdqs51 t af11 pb42b 5 c af11 pb51b 5 c ad14 pb43a 5 t ad14 pb52a 5 t aa15 pb43b 5 c aa15 pb52b 5 c ae12 pb44a 5 pclkt5_0 t ae12 pb53a 5 pclkt5_0 t af12 pb44b 5 pclkc5_0 c af12 pb53b 5 pclkc5_0 c vccio vccio5 5 vccio vccio5 5 gnd gndio5 5 gnd gndio5 5 ad15 pb49a 4 pclkt4_0 t ad15 pb58a 4 pclkt4_0 t vccio vccio4 4 vccio vccio4 4 ac15 pb49b 4 pclkc4_0 c ac15 pb58b 4 pclkc4_0 c ae13 pb50a 4 t ae13 pb59a 4 t af13 pb50b 4 c af13 pb59b 4 c ab17 pb51a 4 bdqs51 t ab17 pb60a 4 bdqs60 t gnd gndio4 4 gnd gndio4 4 y15 pb51b 4 c y15 pb60b 4 c ae14 pb52a 4 t ae14 pb61a 4 t af14 pb52b 4 c af14 pb61b 4 c aa16 pb53a 4 t aa16 pb62a 4 t vccio vccio4 4 vccio vccio4 4 lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-93 pinout information lattice semiconductor latticeecp2/m family data sheet w 15 pb53b 4 c w 15 pb62b 4 c ac17 pb54a 4 t ac17 pb63a 4 t ab16 pb54b 4 c ab16 pb63b 4 c ae15 pb55a 4 t ae15 pb64a 4 t gnd gndio4 4 gnd gndio4 4 af15 pb55b 4 c af15 pb64b 4 c ae16 pb56a 4 t ae16 pb65a 4 t af16 pb56b 4 c af16 pb65b 4 c y16 pb57a 4 t y16 pb66a 4 t ab18 pb57b 4 c ab18 pb66b 4 c ad17 pb58a 4 t ad17 pb67a 4 t ad18 pb58b 4 c ad18 pb67b 4 c vccio vccio4 4 vccio vccio4 4 ac18 pb59a 4 t ac18 pb68a 4 t ad19 pb59b 4 c ad19 pb68b 4 c gnd gndio4 4 gnd gndio4 4 ac19 pb60a 4 bdqs60 t ac19 pb69a 4 bdqs69 t ae17 pb60b 4 c ae17 pb69b 4 c ab19 pb61a 4 t ab19 pb70a 4 t ae19 pb61b 4 c ae19 pb70b 4 c af17 pb62a 4 t af17 pb71a 4 t ae18 pb62b 4 c ae18 pb71b 4 c vccio vccio4 4 vccio vccio4 4 w 16 pb63a 4 t w 16 pb72a 4 t aa17 pb63b 4 c aa17 pb72b 4 c af18 pb64a 4 t af18 pb73a 4 t af19 pb64b 4 c af19 pb73b 4 c gnd gndio4 4 gnd gndio4 4 aa19 pb65a 4 t aa19 pb74a 4 t w 17 pb65b 4 c w 17 pb74b 4 c y19 pb66a 4 t y19 pb75a 4 t y17 pb66b 4 c y17 pb75b 4 c af20 pb67a 4 t af20 pb76a 4 t vccio vccio4 4 vccio vccio4 4 ae20 pb67b 4 c ae20 pb76b 4 c aa20 pb68a 4 t aa20 pb77a 4 t w 18 pb68b 4 c w 18 pb77b 4 c ad20 pb69a 4 bdqs69 t ad20 pb78a 4 bdqs78 t gnd gndio4 4 gnd gndio4 4 ae21 pb69b 4 c ae21 pb78b 4 c af21 pb70a 4 t af21 pb79a 4 t af22 pb70b 4 c af22 pb79b 4 c vccio vccio4 4 vccio vccio4 4 gnd gndio4 4 gnd gndio4 4 lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-94 pinout information lattice semiconductor latticeecp2/m family data sheet ae22 pb74a 4 t ae22 pb92a 4 t ad22 pb74b 4 c ad22 pb92b 4 c af23 pb75a 4 t af23 pb93a 4 t ae23 pb75b 4 c ae23 pb93b 4 c ad23 pb76a 4 t ad23 pb94a 4 t ac23 pb76b 4 c ac23 pb94b 4 c vccio vccio4 4 vccio vccio4 4 ab20 pb77a 4 t ab20 pb95a 4 t ac20 pb77b 4 c ac20 pb95b 4 c gnd gndio4 4 gnd gndio4 4 ab21 pb78a 4 bdqs78 t ab21 pb96a 4 bdqs96 t ac22 pb78b 4 c ac22 pb96b 4 c w 19 pb79a 4 t w 19 pb97a 4 t aa21 pb79b 4 c aa21 pb97b 4 c af24 pb80a 4 t af24 pb98a 4 t ae24 pb80b 4 c ae24 pb98b 4 c vccio vccio4 4 vccio vccio4 4 y20 pb81a 4 t y20 pb99a 4 t ab22 pb81b 4 c ab22 pb99b 4 c y21 pb82a 4 vref2_4 t y21 pb100a 4 vref2_4 t ab23 pb82b 4 vref1_4 c ab23 pb100b 4 vref1_4 c gnd gndio4 4 gnd gndio4 4 ad24 cfg2 8 ad24 cfg2 8 w 20 cfg1 8 w 20 cfg1 8 ac24 cfg0 8 ac24 cfg0 8 v19 programn 8 v19 programn 8 aa22 cclk 8 aa22 cclk 8 ab24 initn 8 ab24 initn 8 ad25 done 8 ad25 done 8 gnd gndio8 8 gnd gndio8 8 w 21 pr77b 8 w riten c w 21 pr90b 8 w riten c y22 pr77a 8 cs1n t y22 pr90a 8 cs1n t ac25 pr76b 8 csn c ac25 pr89b 8 csn c ab25 pr76a 8 d0 t ab25 pr89a 8 d0 t vccio vccio8 8 vccio vccio8 8 ad26 pr75b 8 d1 c ad26 pr88b 8 d1 c ac26 pr75a 8 d2 t ac26 pr88a 8 d2 t y23 pr74b 8 d3 c y23 pr87b 8 d3 c gnd gndio8 8 gnd gndio8 8 w 22 pr74a 8 d4 t w 22 pr87a 8 d4 t aa25 pr73b 8 d5 c aa25 pr86b 8 d5 c ab26 pr73a 8 d6 t ab26 pr86a 8 d6 t w 23 pr72b 8 d7 c w 23 pr85b 8 d7 c vccio vccio8 8 vccio vccio8 8 lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-95 pinout information lattice semiconductor latticeecp2/m family data sheet v22 pr72a 8 di/csspi0n t v22 pr85a 8 di/csspi0n t y24 pr71b 8 dout/cson c y24 pr84b 8 dout/cson c y25 pr71a 8 busy/sispi t y25 pr84a 8 busy/sispi t w 24 pr70b 3 c w 24 pr83b 3 c gnd gndio3 3 gnd gndio3 3 v23 pr70a 3 t v23 pr83a 3 t aa26 pr69b 3 c (lvds)* aa26 pr82b 3 c (lvds)* y26 pr69a 3 t (lvds)* y26 pr82a 3 t (lvds)* u21 pr68b 3 c u21 pr81b 3 c vccio vccio3 3 vccio vccio3 3 u19 pr68a 3 t u19 pr81a 3 t w 25 pr67b 3 c (lvds)* w 25 pr80b 3 c (lvds)* w 26 pr67a 3 rdqs67 t (lvds)* w 26 pr80a 3 rdqs80 t (lvds)* gnd gndio3 3 gnd gndio3 3 v24 pr66b 3 c v24 pr79b 3 c v25 pr66a 3 t v25 pr79a 3 t v26 pr65b 3 c (lvds)* v26 pr78b 3 c (lvds)* u26 pr65a 3 t (lvds)* u26 pr78a 3 t (lvds)* vccio vccio3 3 vccio vccio3 3 u22 pr64b 3 rlm0_gpllc_fb_a c u22 pr77b 3 rlm0_gpllc_fb_a c u23 pr64a 3 rlm0_gpllt_fb_a t u23 pr77a 3 rlm0_gpllt_fb_a t u24 pr63b 3 rlm0_gpllc_in_a** c (lvds)* u24 pr76b 3 rlm0_gpllc_in_a** c (lvds)* u25 pr63a 3 rlm0_gpllt_in_a** t (lvds)* u25 pr76a 3 rlm0_gpllt_in_a** t (lvds)* r20 rlm0_pllcap 3 r20 rlm0_pllcap 3 p18 vccpll 3 p18 vccpll - t19 pr61b 3 rlm0_gdllc_fb_a c t19 pr74b 3 rlm0_gdllc_fb_a c u20 pr61a 3 rlm0_gdllt_fb_a t u20 pr74a 3 rlm0_gdllt_fb_a t gnd gndio3 3 gnd gndio3 3 t25 pr60b 3 rlm0_gdllc_in_a** c (lvds)* t25 pr73b 3 rlm0_gdllc_in_a** c (lvds)* t26 pr60a 3 rlm0_gdllt_in_a** t (lvds)* t26 pr73a 3 rlm0_gdllt_in_a** t (lvds)* t20 pr59b 3 c t20 pr72b 3 c t22 pr59a 3 t t22 pr72a 3 t vccio vccio3 3 vccio vccio3 3 r26 pr58b 3 c (lvds)* r26 pr71b 3 c (lvds)* r25 pr58a 3 rdqs58 t (lvds)* r25 pr71a 3 rdqs71 t (lvds)* r22 pr57b 3 c r22 pr70b 3 c gnd gndio3 3 gnd gndio3 3 t21 pr57a 3 t t21 pr70a 3 t p26 pr56b 3 c (lvds)* p26 pr69b 3 c (lvds)* p25 pr56a 3 t (lvds)* p25 pr69a 3 t (lvds)* r24 pr55b 3 c r24 pr68b 3 c vccio vccio3 3 vccio vccio3 3 r23 pr55a 3 t r23 pr68a 3 t p20 pr54b 3 c (lvds)* p20 pr67b 3 c (lvds)* lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-96 pinout information lattice semiconductor latticeecp2/m family data sheet r19 pr54a 3 t (lvds)* r19 pr67a 3 t (lvds)* p21 pr53b 3 c p21 pr66b 3 c gnd gndio3 3 gnd gndio3 3 p19 pr53a 3 t p19 pr66a 3 t p23 pr52b 3 c (lvds)* p23 pr65b 3 c (lvds)* p22 pr52a 3 t (lvds)* p22 pr65a 3 t (lvds)* n22 pr51b 3 c n22 pr64b 3 c vccio vccio3 3 vccio vccio3 3 r21 pr51a 3 t r21 pr64a 3 t n26 pr50b 3 c (lvds)* n26 pr63b 3 c (lvds)* n25 pr50a 3 rdqs50 t (lvds)* n25 pr63a 3 rdqs63 t (lvds)* gnd gndio3 3 gnd gndio3 3 n19 pr49b 3 c n19 pr62b 3 c n20 pr49a 3 t n20 pr62a 3 t m26 pr48b 3 c (lvds)* m26 pr61b 3 c (lvds)* m25 pr48a 3 t (lvds)* m25 pr61a 3 t (lvds)* vccio vccio3 3 vccio vccio3 3 n18 pr47b 3 vref2_3 c n18 pr60b 3 vref2_3 c n21 pr47a 3 vref1_3 t n21 pr60a 3 vref1_3 t l26 pr46b 3 pclkc3_0 c (lvds)* l26 pr59b 3 pclkc3_0 c (lvds)* l25 pr46a 3 pclkt3_0 t (lvds)* l25 pr59a 3 pclkt3_0 t (lvds)* n24 pr44b 2 pclkc2_0 c n24 pr57b 2 pclkc2_0 c m23 pr44a 2 pclkt2_0 t m23 pr57a 2 pclkt2_0 t gnd gndio2 2 gnd gndio2 2 l21 pr43b 2 c (lvds)* l21 pr56b 2 c (lvds)* k22 pr43a 2 t (lvds)* k22 pr56a 2 t (lvds)* m24 pr42b 2 c m24 pr55b 2 c n23 pr42a 2 t n23 pr55a 2 t vccio vccio2 2 vccio vccio2 2 k26 pr41b 2 c (lvds)* k26 pr54b 2 c (lvds)* k25 pr41a 2 rdqs41 t (lvds)* k25 pr54a 2 rdqs54 t (lvds)* m20 pr40b 2 c m20 pr53b 2 c gnd gndio2 2 gnd gndio2 2 m19 pr40a 2 t m19 pr53a 2 t l22 pr39b 2 c (lvds)* l22 pr52b 2 c (lvds)* m22 pr39a 2 t (lvds)* m22 pr52a 2 t (lvds)* k21 pr38b 2 c k21 pr51b 2 c vccio vccio2 2 vccio vccio2 2 m21 pr38a 2 t m21 pr51a 2 t k24 pr37b 2 c (lvds)* k24 pr50b 2 c (lvds)* j24 pr37a 2 t (lvds)* j24 pr50a 2 t (lvds)* gnd gndio2 2 gnd gndio2 2 vccio vccio2 2 vccio vccio2 2 gnd gndio2 2 gnd gndio2 2 lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-97 pinout information lattice semiconductor latticeecp2/m family data sheet vccio vccio2 2 vccio vccio2 2 l20 vccpll 2 l20 nc - gnd gndio2 2 gnd gndio2 2 j26 pr26b 2 rum0_spllc_fb_a c j26 pr39b 2 rum0_spllc_fb_a c j25 pr26a 2 rum0_spllt_fb_a t j25 pr39a 2 rum0_spllt_fb_a t j23 pr25b 2 rum0_spllc_in_a c j23 pr38b 2 rum0_spllc_in_a c k23 pr25a 2 rum0_spllt_in_a t k23 pr38a 2 rum0_spllt_in_a t vccio vccio2 2 vccio vccio2 2 h26 pr24b 2 c (lvds)* h26 pr37b 2 c (lvds)* h25 pr24a 2 t (lvds)* h25 pr37a 2 t (lvds)* h24 pr23b 2 c h24 pr36b 2 c gnd gndio2 2 gnd gndio2 2 h23 pr23a 2 t h23 pr36a 2 t vccio vccio2 2 vccio vccio2 2 g26 pr19b 2 c g26 pr32b 2 c gnd gndio2 2 gnd gndio2 2 g25 pr19a 2 t g25 pr32a 2 t f26 pr18b 2 c (lvds)* f26 pr31b 2 c (lvds)* f25 pr18a 2 t (lvds)* f25 pr31a 2 t (lvds)* k20 pr17b 2 c k20 pr30b 2 c vccio vccio2 2 vccio vccio2 2 l19 pr17a 2 t l19 pr30a 2 t e26 pr16b 2 c (lvds)* e26 pr29b 2 c (lvds)* e25 pr16a 2 rdqs16 t (lvds)* e25 pr29a 2 rdqs29 t (lvds)* gnd gndio2 2 gnd gndio2 2 j22 pr15b 2 c j22 pr28b 2 c h22 pr15a 2 t h22 pr28a 2 t g24 pr14b 2 c (lvds)* g24 pr27b 2 c (lvds)* g23 pr14a 2 t (lvds)* g23 pr27a 2 t (lvds)* vccio vccio2 2 vccio vccio2 2 k19 pr13b 2 c k19 pr26b 2 c j19 pr13a 2 t j19 pr26a 2 t d26 pr12b 2 c (lvds)* d26 pr25b 2 c (lvds)* c26 pr12a 2 t (lvds)* c26 pr25a 2 t (lvds)* f22 pr11b 2 c f22 pr24b 2 c e24 pr11a 2 t e24 pr24a 2 t gnd gndio2 2 gnd gndio2 2 d25 pr10b 2 c (lvds)* d25 pr23b 2 c (lvds)* c25 pr10a 2 t (lvds)* c25 pr23a 2 t (lvds)* d24 pr9b 2 c d24 pr22b 2 c b25 pr9a 2 t b25 pr22a 2 t vccio vccio2 2 vccio vccio2 2 h21 pr8b 2 c (lvds)* h21 pr21b 2 c (lvds)* g22 pr8a 2 rdqs8 t (lvds)* g22 pr21a 2 rdqs21 t (lvds)* lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-98 pinout information lattice semiconductor latticeecp2/m family data sheet b24 pr7b 2 c b24 pr20b 2 c gnd gndio2 2 gnd gndio2 2 c24 pr7a 2 t c24 pr20a 2 t d23 pr6b 2 c (lvds)* d23 pr19b 2 c (lvds)* c23 pr6a 2 t (lvds)* c23 pr19a 2 t (lvds)* g21 pr5b 2 c g21 pr18b 2 c vccio vccio2 2 vccio vccio2 2 h20 pr5a 2 t h20 pr18a 2 t gnd gndio2 2 gnd gndio2 2 e22 pr2b 2 vref2_2 c (lvds)* e22 pr2b 2 vref2_2 c (lvds)* f21 pr2a 2 vref1_2 t (lvds)* f21 pr2a 2 vref1_2 t (lvds)* e23 pt82b 1 vref2_1 c e23 pt100b 1 vref2_1 c gnd gndio1 1 gnd gndio1 1 d22 pt82a 1 vref1_1 t d22 pt100a 1 vref1_1 t g20 pt81b 1 c g20 pt99b 1 c j18 pt81a 1 t j18 pt99a 1 t f20 pt80b 1 c f20 pt98b 1 c vccio vccio1 1 vccio vccio1 1 h19 pt80a 1 t h19 pt98a 1 t a24 pt79b 1 c a24 pt97b 1 c a23 pt79a 1 t a23 pt97a 1 t e21 pt78b 1 c e21 pt96b 1 c f19 pt78a 1 t f19 pt96a 1 t c22 pt77b 1 c c22 pt95b 1 c gnd gndio1 1 gnd gndio1 1 e20 pt77a 1 t e20 pt95a 1 t b22 pt76b 1 c b22 pt94b 1 c vccio vccio1 1 vccio vccio1 1 b23 pt76a 1 t b23 pt94a 1 t c20 pt75b 1 c c20 pt93b 1 c d20 pt75a 1 t d20 pt93a 1 t a22 pt74b 1 c a22 pt92b 1 c a21 pt74a 1 t a21 pt92a 1 t gnd gndio1 1 gnd gndio1 1 e19 pt71b 1 c e19 pt85b 1 c c19 pt71a 1 t c19 pt85a 1 t vccio vccio1 1 vccio vccio1 1 b21 pt70b 1 c b21 pt79b 1 c b20 pt70a 1 t b20 pt79a 1 t d19 pt69b 1 c d19 pt78b 1 c b19 pt69a 1 t b19 pt78a 1 t gnd gndio1 1 gnd gndio1 1 g17 pt68b 1 c g17 pt77b 1 c e18 pt68a 1 t e18 pt77a 1 t lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-99 pinout information lattice semiconductor latticeecp2/m family data sheet g19 pt67b 1 c g19 pt76b 1 c f17 pt67a 1 t f17 pt76a 1 t vccio vccio1 1 vccio vccio1 1 a20 pt66b 1 c a20 pt75b 1 c a19 pt66a 1 t a19 pt75a 1 t e17 pt65b 1 c e17 pt74b 1 c d18 pt65a 1 t d18 pt74a 1 t b18 pt64b 1 c b18 pt73b 1 c gnd gndio1 1 gnd gndio1 1 a18 pt64a 1 t a18 pt73a 1 t e16 pt63b 1 c e16 pt72b 1 c g16 pt63a 1 t g16 pt72a 1 t f16 pt62b 1 c f16 pt71b 1 c vccio vccio1 1 vccio vccio1 1 h18 pt62a 1 t h18 pt71a 1 t a17 pt61b 1 c a17 pt70b 1 c b17 pt61a 1 t b17 pt70a 1 t c18 pt60b 1 c c18 pt69b 1 c b16 pt60a 1 t b16 pt69a 1 t c17 pt59b 1 c c17 pt68b 1 c gnd gndio1 1 gnd gndio1 1 d17 pt59a 1 t d17 pt68a 1 t e15 pt58b 1 c e15 pt67b 1 c vccio vccio1 1 vccio vccio1 1 g15 pt58a 1 t g15 pt67a 1 t a16 pt57b 1 c a16 pt66b 1 c b15 pt57a 1 t b15 pt66a 1 t d15 pt56b 1 c d15 pt65b 1 c f15 pt56a 1 t f15 pt65a 1 t a14 pt55b 1 c a14 pt64b 1 c b14 pt55a 1 t b14 pt64a 1 t gnd gndio1 1 gnd gndio1 1 c15 pt54b 1 c c15 pt63b 1 c a15 pt54a 1 t a15 pt63a 1 t a13 pt53b 1 c a13 pt62b 1 c b13 pt53a 1 t b13 pt62a 1 t vccio vccio1 1 vccio vccio1 1 h17 pt52b 1 c h17 pt61b 1 c h15 pt52a 1 t h15 pt61a 1 t d13 pt51b 1 c d13 pt60b 1 c c14 pt51a 1 t c14 pt60a 1 t gnd gndio1 1 gnd gndio1 1 g14 pt50b 1 c g14 pt59b 1 c e14 pt50a 1 t e14 pt59a 1 t lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-100 pinout information lattice semiconductor latticeecp2/m family data sheet a12 pt49b 1 c a12 pt58b 1 c b12 pt49a 1 t b12 pt58a 1 t vccio vccio1 1 vccio vccio1 1 f14 pt48b 1 pclkc1_0 c f14 pt57b 1 pclkc1_0 c d14 pt48a 1 pclkt1_0 t d14 pt57a 1 pclkt1_0 t h16 xres 1 h16 xres 1 h14 pt46b 0 pclkc0_0 c h14 pt55b 0 pclkc0_0 c gnd gndio0 0 gnd gndio0 0 h13 pt46a 0 pclkt0_0 t h13 pt55a 0 pclkt0_0 t a11 pt45b 0 c a11 pt54b 0 c b11 pt45a 0 t b11 pt54a 0 t c13 pt44b 0 c c13 pt53b 0 c vccio vccio0 0 vccio vccio0 0 e13 pt44a 0 t e13 pt53a 0 t d12 pt43b 0 c d12 pt52b 0 c f13 pt43a 0 t f13 pt52a 0 t a10 pt42b 0 c a10 pt51b 0 c b10 pt42a 0 t b10 pt51a 0 t c12 pt41b 0 c c12 pt50b 0 c gnd gndio0 0 gnd gndio0 0 c10 pt41a 0 t c10 pt50a 0 t g13 pt40b 0 c g13 pt49b 0 c vccio vccio0 0 vccio vccio0 0 h12 pt40a 0 t h12 pt49a 0 t a9 pt39b 0 c a9 pt48b 0 c b9 pt39a 0 t b9 pt48a 0 t e12 pt38b 0 c e12 pt47b 0 c g12 pt38a 0 t g12 pt47a 0 t a8 pt37b 0 c a8 pt46b 0 c b8 pt37a 0 t b8 pt46a 0 t gnd gndio0 0 gnd gndio0 0 e11 pt36b 0 c e11 pt45b 0 c c9 pt36a 0 t c9 pt45a 0 t a7 pt35b 0 c a7 pt44b 0 c b7 pt35a 0 t b7 pt44a 0 t vccio vccio0 0 vccio vccio0 0 f12 pt34b 0 c f12 pt43b 0 c d10 pt34a 0 t d10 pt43a 0 t h11 pt33b 0 c h11 pt42b 0 c g11 pt33a 0 t g11 pt42a 0 t gnd gndio0 0 gnd gndio0 0 a6 pt32b 0 c a6 pt41b 0 c b6 pt32a 0 t b6 pt41a 0 t d8 pt31b 0 c d8 pt40b 0 c lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-101 pinout information lattice semiconductor latticeecp2/m family data sheet c8 pt31a 0 t c8 pt40a 0 t vccio vccio0 0 vccio vccio0 0 f11 pt30b 0 c f11 pt39b 0 c e10 pt30a 0 t e10 pt39a 0 t e9 pt29b 0 c e9 pt38b 0 c d9 pt29a 0 t d9 pt38a 0 t g10 pt28b 0 c g10 pt37b 0 c gnd gndio0 0 gnd gndio0 0 h10 pt28a 0 t h10 pt37a 0 t a5 pt27b 0 c a5 pt36b 0 c b5 pt27a 0 t b5 pt36a 0 t c7 pt26b 0 c c7 pt35b 0 c vccio vccio0 0 vccio vccio0 0 d7 pt26a 0 t d7 pt35a 0 t e8 pt25b 0 c e8 pt34b 0 c f10 pt25a 0 t f10 pt34a 0 t f8 pt24b 0 c f8 pt33b 0 c h9 pt24a 0 t h9 pt33a 0 t c5 pt23b 0 c c5 pt32b 0 c gnd gndio0 0 gnd gndio0 0 d5 pt23a 0 t d5 pt32a 0 t b4 pt22b 0 b4 pt31b 0 vccio vccio0 0 vccio vccio0 0 gnd gndio0 0 gnd gndio0 0 vccio vccio0 0 vccio vccio0 0 gnd gndio0 0 gnd gndio0 0 vccio vccio0 0 vccio vccio0 0 c4 pt10b 0 c c4 pt10b 0 c gnd gndio0 0 gnd gndio0 0 c3 pt10a 0 t c3 pt10a 0 t a4 pt9b 0 c a4 pt9b 0 c a3 pt9a 0 t a3 pt9a 0 t b3 pt8b 0 c b3 pt8b 0 c vccio vccio0 0 vccio vccio0 0 b2 pt8a 0 t b2 pt8a 0 t d4 pt7b 0 c d4 pt7b 0 c d3 pt7a 0 t d3 pt7a 0 t c2 pt6b 0 c c2 pt6b 0 c c1 pt6a 0 t c1 pt6a 0 t g8 pt5b 0 c g8 pt5b 0 c gnd gndio0 0 gnd gndio0 0 g7 pt5a 0 t g7 pt5a 0 t e7 pt4b 0 c e7 pt4b 0 c vccio vccio0 0 vccio vccio0 0 lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-102 pinout information lattice semiconductor latticeecp2/m family data sheet f7 pt4a 0 t f7 pt4a 0 t e6 pt3b 0 c e6 pt3b 0 c e5 pt3a 0 t e5 pt3a 0 t g6 pt2b 0 vref2_0 c g6 pt2b 0 vref2_0 c g5 pt2a 0 vref1_0 t g5 pt2a 0 vref1_0 t l12 vcc - l12 vcc - l13 vcc - l13 vcc - l14 vcc - l14 vcc - l15 vcc - l15 vcc - m11 vcc - m11 vcc - m12 vcc - m12 vcc - m15 vcc - m15 vcc - m16 vcc - m16 vcc - n11 vcc - n11 vcc - n16 vcc - n16 vcc - p11 vcc - p11 vcc - p16 vcc - p16 vcc - r11 vcc - r11 vcc - r12 vcc - r12 vcc - r15 vcc - r15 vcc - r16 vcc - r16 vcc - t12 vcc - t12 vcc - t13 vcc - t13 vcc - t14 vcc - t14 vcc - t15 vcc - t15 vcc - d11 vccio0 0 d11 vccio0 0 d6 vccio0 0 d6 vccio0 0 g9 vccio0 0 g9 vccio0 0 k12 vccio0 0 k12 vccio0 0 j12 vccio0 0 j12 vccio0 0 d16 vccio1 1 d16 vccio1 1 d21 vccio1 1 d21 vccio1 1 g18 vccio1 1 g18 vccio1 1 j15 vccio1 1 j15 vccio1 1 k15 vccio1 1 k15 vccio1 1 f23 vccio2 2 f23 vccio2 2 j20 vccio2 2 j20 vccio2 2 l23 vccio2 2 l23 vccio2 2 m17 vccio2 2 m17 vccio2 2 m18 vccio2 2 m18 vccio2 2 aa23 vccio3 3 aa23 vccio3 3 r17 vccio3 3 r17 vccio3 3 r18 vccio3 3 r18 vccio3 3 t23 vccio3 3 t23 vccio3 3 lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-103 pinout information lattice semiconductor latticeecp2/m family data sheet v20 vccio3 3 v20 vccio3 3 ac16 vccio4 4 ac16 vccio4 4 ac21 vccio4 4 ac21 vccio4 4 u15 vccio4 4 u15 vccio4 4 v15 vccio4 4 v15 vccio4 4 y18 vccio4 4 y18 vccio4 4 ac11 vccio5 5 ac11 vccio5 5 ac6 vccio5 5 ac6 vccio5 5 u12 vccio5 5 u12 vccio5 5 v12 vccio5 5 v12 vccio5 5 y9 vccio5 5 y9 vccio5 5 aa4 vccio6 6 aa4 vccio6 6 r10 vccio6 6 r10 vccio6 6 r9 vccio6 6 r9 vccio6 6 t4 vccio6 6 t4 vccio6 6 v7 vccio6 6 v7 vccio6 6 f4 vccio7 7 f4 vccio7 7 j7 vccio7 7 j7 vccio7 7 l4 vccio7 7 l4 vccio7 7 m10 vccio7 7 m10 vccio7 7 m9 vccio7 7 m9 vccio7 7 ae25 vccio8 8 ae25 vccio8 8 v18 vccio8 8 v18 vccio8 8 j10 vccaux - j10 vccaux - j11 vccaux - j11 vccaux - j16 vccaux - j16 vccaux - j17 vccaux - j17 vccaux - k18 vccaux - k18 vccaux - k9 vccaux - k9 vccaux - l18 vccaux - l18 vccaux - l9 vccaux - l9 vccaux - t18 vccaux - t18 vccaux - t9 vccaux - t9 vccaux - u18 vccaux - u18 vccaux - u9 vccaux - u9 vccaux - v10 vccaux - v10 vccaux - v11 vccaux - v11 vccaux - v16 vccaux - v16 vccaux - v17 vccaux - v17 vccaux - a2 gnd - a2 gnd - a25 gnd - a25 gnd - aa18 gnd - aa18 gnd - aa24 gnd - aa24 gnd - aa3 gnd - aa3 gnd - lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-104 pinout information lattice semiconductor latticeecp2/m family data sheet aa9 gnd - aa9 gnd - ad11 gnd - ad11 gnd - ad16 gnd - ad16 gnd - ad21 gnd - ad21 gnd - ad6 gnd - ad6 gnd - ae1 gnd - ae1 gnd - ae26 gnd - ae26 gnd - af2 gnd - af2 gnd - af25 gnd - af25 gnd - b1 gnd - b1 gnd - b26 gnd - b26 gnd - c11 gnd - c11 gnd - c16 gnd - c16 gnd - c21 gnd - c21 gnd - c6 gnd - c6 gnd - f18 gnd - f18 gnd - f24 gnd - f24 gnd - f3 gnd - f3 gnd - f9 gnd - f9 gnd - j13 gnd - j13 gnd - j14 gnd - j14 gnd - j21 gnd - j21 gnd - j6 gnd - j6 gnd - k10 gnd - k10 gnd - k11 gnd - k11 gnd - k13 gnd - k13 gnd - k14 gnd - k14 gnd - k16 gnd - k16 gnd - k17 gnd - k17 gnd - l10 gnd - l10 gnd - l11 gnd - l11 gnd - l16 gnd - l16 gnd - l17 gnd - l17 gnd - l24 gnd - l24 gnd - l3 gnd - l3 gnd - m13 gnd - m13 gnd - m14 gnd - m14 gnd - n10 gnd - n10 gnd - n12 gnd - n12 gnd - n13 gnd - n13 gnd - n14 gnd - n14 gnd - n15 gnd - n15 gnd - n17 gnd - n17 gnd - p10 gnd - p10 gnd - lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-105 pinout information lattice semiconductor latticeecp2/m family data sheet p12 gnd - p12 gnd - p13 gnd - p13 gnd - p14 gnd - p14 gnd - p15 gnd - p15 gnd - p17 gnd - p17 gnd - r13 gnd - r13 gnd - r14 gnd - r14 gnd - t10 gnd - t10 gnd - t11 gnd - t11 gnd - t16 gnd - t16 gnd - t17 gnd - t17 gnd - t24 gnd - t24 gnd - t3 gnd - t3 gnd - u10 gnd - u10 gnd - u11 gnd - u11 gnd - u13 gnd - u13 gnd - u14 gnd - u14 gnd - u16 gnd - u16 gnd - u17 gnd - u17 gnd - v13 gnd - v13 gnd - v14 gnd - v14 gnd - v21 gnd - v21 gnd - v6 gnd - v6 gnd - m3 nc - m3 nc - n6 nc - p24 nc - p24 nc - n6 nc - * supports true lvds. other differential signals must be emulated with external resistors. ** these dedicated input pins can be used for gplls or gdlls within the respective quadrant. lfe2-50e/50se and lfe2-70e/70se logic signal connections: 672 fpbga (cont.) lfe2-50e/50se lfe2-70e/70se ball number ball function bank dual function differential ball number ball function bank dual function differential
4-106 pinout information lattice semiconductor latticeecp2/m family data sheet lfe2-70e/70se logic signal connections: 900 fpbga ball number ball function bank dual function differential f4 pl2a 7 vref2_7 t (lvds)* f3 pl2b 7 vref1_7 c (lvds)* h4 pl3a 7 t g5 pl3b 7 c gnd gndio 7 d2 pl4a 7 t (lvds)* d1 pl4b 7 c (lvds)* e2 pl5a 7 t e1 pl5b 7 c gnd gndio 7 f1 pl14a 7 lum1_spllt_in_a t (lvds)* f2 pl14b 7 lum1_spllc_in_a c (lvds)* g1 pl15a 7 lum1_spllt_fb_a t g2 pl15b 7 lum1_spllc_fb_a c gnd gndio 7 h8 pl18a 7 t h6 pl18b 7 c g4 pl19a 7 t (lvds)* g3 pl19b 7 c (lvds)* h7 pl20a 7 t h5 pl20b 7 c gnd gndio 7 h2 pl21a 7 ldqs21 t (lvds)* h1 pl21b 7 c (lvds)* j6 pl22a 7 t j8 pl22b 7 c j2 pl23a 7 t (lvds)* j1 pl23b 7 c (lvds)* j5 pl24a 7 t gnd gndio 7 j7 pl24b 7 c j4 pl25a 7 t (lvds)* j3 pl25b 7 c (lvds)* k6 pl26a 7 t k8 pl26b 7 c k2 pl27a 7 t (lvds)* k1 pl27b 7 c (lvds)* k5 pl28a 7 t k7 pl28b 7 c gnd gndio 7 k4 pl29a 7 ldqs29 t (lvds)* k3 pl29b 7 c (lvds)* l8 pl30a 7 t
4-107 pinout information lattice semiconductor latticeecp2/m family data sheet l6 pl30b 7 c l2 pl31a 7 t (lvds)* l1 pl31b 7 c (lvds)* l7 pl32a 7 t gnd gndio 7 l5 pl32b 7 c l4 pl33a 7 t (lvds)* l3 pl33b 7 c (lvds)* m8 pl34a 7 t m6 pl34b 7 c m2 pl35a 7 t (lvds)* m1 pl35b 7 c (lvds)* m7 pl36a 7 t m5 pl36b 7 c gnd gndio 7 m4 pl37a 7 ldqs37 t (lvds)* m3 pl37b 7 c (lvds)* n6 pl38a 7 lum0_spllt_in_a t n8 pl38b 7 lum0_spllc_in_a c n5 pl39a 7 lum0_spllt_fb_a t n7 pl39b 7 lum0_spllc_fb_a c gnd gndio 7 t9 pl50a 7 r9 pl51a 7 t p7 pl51b 7 c n2 pl52a 7 t (lvds)* n1 pl52b 7 c (lvds)* p6 pl53a 7 t p5 pl53b 7 c gnd gndio 7 p4 pl54a 7 ldqs54 t (lvds)* p3 pl54b 7 c (lvds)* r6 pl55a 7 t r8 pl55b 7 c p2 pl56a 7 t (lvds)* p1 pl56b 7 c (lvds)* r5 pl57a 7 pclkt7_0 t gnd gndio 7 r7 pl57b 7 pclkc7_0 c r4 pl59a 6 pclkt6_0 t (lvds)* r3 pl59b 6 pclkc6_0 c (lvds)* t5 pl60a 6 vref2_6 t t7 pl60b 6 vref1_6 c t3 pl61a 6 t (lvds)* lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-108 pinout information lattice semiconductor latticeecp2/m family data sheet t4 pl61b 6 c (lvds)* t6 pl62a 6 t t8 pl62b 6 c t2 pl63a 6 ldqs63 t (lvds)* gnd gndio 6 t1 pl63b 6 c (lvds)* u7 pl64a 6 t u5 pl64b 6 c u4 pl65a 6 t (lvds)* u3 pl65b 6 c (lvds)* u8 pl66a 6 t u6 pl66b 6 c gnd gndio 6 u2 pl67a 6 t (lvds)* u1 pl67b 6 c (lvds)* v7 pl68a 6 t v5 pl68b 6 c v2 pl69a 6 t (lvds)* v1 pl69b 6 c (lvds)* v8 pl70a 6 t v6 pl70b 6 c gnd gndio 6 w 1 pl71a 6 ldqs71 t (lvds)* w 2 pl71b 6 c (lvds)* w 5 pl72a 6 t w 7 pl72b 6 c w 4 pl73a 6 llm0_gdllt_in_a** t (lvds)* w 3 pl73b 6 llm0_gdllc_in_a** c (lvds)* w 6 pl74a 6 llm0_gdllt_fb_a t gnd gndio 6 w 8 pl74b 6 llm0_gdllc_fb_d c y8 llm0_pllcap 6 y1 pl76a 6 llm0_gpllt_in_a** t (lvds)* y2 pl76b 6 llm0_gpllc_in_a** c (lvds)* y5 pl77a 6 llm0_gpllt_fb_a t y6 pl77b 6 llm0_gpllc_fb_a c y4 pl78a 6 t (lvds)* y3 pl78b 6 c (lvds)* aa6 pl79a 6 t aa8 pl79b 6 c aa2 pl80a 6 ldqs80 t (lvds)* gnd gndio 6 aa1 pl80b 6 c (lvds)* aa7 pl81a 6 t lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-109 pinout information lattice semiconductor latticeecp2/m family data sheet aa5 pl81b 6 c aa4 pl82a 6 t (lvds)* aa3 pl82b 6 c (lvds)* ab7 pl83a 6 t ab5 pl83b 6 c gnd gndio 6 ab2 pl84a 6 t (lvds)* ab1 pl84b 6 c (lvds)* ab8 pl85a 6 t ab6 pl85b 6 c ab4 pl86a 6 t (lvds)* ab3 pl86b 6 c (lvds)* ac7 pl87a 6 t ac5 pl87b 6 c gnd gndio 6 ac2 pl88a 6 ldqs88 t (lvds)* ac1 pl88b 6 c (lvds)* ac6 pl89a 6 t ad6 pl89b 6 c ad1 pl90a 6 t (lvds)* ad2 pl90b 6 c (lvds)* ad7 pl91a 6 t gnd gndio 6 ab9 pl91b 6 c ad5 tck - ae7 tdi - ad4 tms - aa9 tdo - ad3 vccj - ac8 pb2a 5 vref2_5 t ae8 pb2b 5 vref1_5 c ad8 pb3a 5 t af8 pb3b 5 c ag7 pb4a 5 t ah7 pb4b 5 c ac9 pb5a 5 t ae9 pb5b 5 c ad9 pb6a 5 bdqs6 t gnd gndio 5 af9 pb6b 5 c ab10 pb7a 5 t aa10 pb7b 5 c aj7 pb8a 5 t ak7 pb8b 5 c lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-110 pinout information lattice semiconductor latticeecp2/m family data sheet ac10 pb9a 5 t ae10 pb9b 5 c aj8 pb10a 5 t gnd gndio 5 ak8 pb10b 5 c af6 pb11a 5 t af7 pb11b 5 c ag5 pb12a 5 t ah5 pb12b 5 c ag6 pb13a 5 t ah6 pb13b 5 c aj4 pb14a 5 t ak4 pb14b 5 c gnd gndio 5 aj5 pb15a 5 bdqs15 t ak5 pb15b 5 c aj6 pb16a 5 t ak6 pb16b 5 c gnd gndio 5 ad10 pb29a 5 t af10 pb29b 5 c ac11 pb30a 5 t ad11 pb30b 5 c ag9 pb31a 5 t ah9 pb31b 5 c ae11 pb32a 5 t ag10 pb32b 5 c gnd gndio 5 aj9 pb33a 5 bdqs33 t ak9 pb33b 5 c af11 pb34a 5 t ah10 pb34b 5 c ac12 pb35a 5 t ae12 pb35b 5 c ad12 pb36a 5 t af12 pb36b 5 c aj10 pb37a 5 t ak10 pb37b 5 c gnd gndio 5 ag11 pb38a 5 t ah11 pb38b 5 c ae13 pb39a 5 t ac13 pb39b 5 c af13 pb40a 5 t lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-111 pinout information lattice semiconductor latticeecp2/m family data sheet ad13 pb40b 5 c aj11 pb41a 5 t ak11 pb41b 5 c ad14 pb42a 5 bdqs42 t gnd gndio 5 ac14 pb42b 5 c ag12 pb43a 5 t ae14 pb43b 5 c aj12 pb44a 5 t ak12 pb44b 5 c ah12 pb45a 5 t af14 pb45b 5 c aj13 pb46a 5 t gnd gndio 5 ak13 pb46b 5 c ab15 pb47a 5 t ad15 pb47b 5 c ae15 pb48a 5 t af15 pb48b 5 c ag15 pb49a 5 t ag14 pb49b 5 c ah15 pb50a 5 t ah14 pb50b 5 c gnd gndio 5 aj14 pb51a 5 bdqs51 t ak14 pb51b 5 c ad16 pb52a 5 t af16 pb52b 5 c aj15 pb53a 5 pclkt5_0 t ak15 pb53b 5 pclkc5_0 c gnd gndio 5 ae16 pb58a 4 pclkt4_0 t ac15 pb58b 4 pclkc4_0 c aj16 pb59a 4 t ak16 pb59b 4 c ac16 pb60a 4 bdqs60 t gnd gndio 4 ab16 pb60b 4 c ah17 pb61a 4 t ag17 pb61b 4 c af17 pb62a 4 t ad17 pb62b 4 c ae17 pb63a 4 t ac17 pb63b 4 c lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-112 pinout information lattice semiconductor latticeecp2/m family data sheet aj17 pb64a 4 t gnd gndio 4 ak17 pb64b 4 c ak18 pb65a 4 t aj18 pb65b 4 c ad18 pb66a 4 t af18 pb66b 4 c ac18 pb67a 4 t ae18 pb67b 4 c ag19 pb68a 4 t ah19 pb68b 4 c gnd gndio 4 ae19 pb69a 4 bdqs69 t af19 pb69b 4 c ac19 pb70a 4 t ad19 pb70b 4 c aj19 pb71a 4 t ak19 pb71b 4 c af20 pb72a 4 t ah20 pb72b 4 c ae20 pb73a 4 t ag20 pb73b 4 c gnd gndio 4 ad20 pb74a 4 t ac20 pb74b 4 c ah21 pb75a 4 t af21 pb75b 4 c aj20 pb76a 4 t ak20 pb76b 4 c ag21 pb77a 4 t ae21 pb77b 4 c ad21 pb78a 4 bdqs78 t gnd gndio 4 ac21 pb78b 4 c ad22 pb79a 4 t ab21 pb79b 4 c aj21 pb80a 4 t ak21 pb80b 4 c gnd gndio 4 aj25 pb87a 4 bdqs87 t ak24 pb87b 4 c aj24 pb88a 4 t ak25 pb88b 4 c ah24 pb89a 4 t lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-113 pinout information lattice semiconductor latticeecp2/m family data sheet ah25 pb89b 4 c aj26 pb90a 4 t ak26 pb90b 4 c af25 pb91a 4 t ag25 pb91b 4 c gnd gndio 4 ak22 pb92a 4 t aj22 pb92b 4 c ae22 pb93a 4 t af22 pb93b 4 c ag22 pb94a 4 t ah22 pb94b 4 c ag24 pb95a 4 t ag23 pb95b 4 c ae23 pb96a 4 bdqs96 gnd gndio 4 ac22 pb97a 4 aj23 pb98a 4 t ak23 pb98b 4 c ad24 pb99a 4 t af24 pb99b 4 c ac23 pb100a 4 vref2_4 t gnd gndio 4 ae24 pb100b 4 vref1_4 c ae25 cfg2 8 ab22 cfg1 8 ae26 cfg0 8 aa22 programn 8 ad25 cclk 8 ad26 initn 8 ac24 done 8 gnd gndio 4 ac25 pr90b 8 w riten c ae27 pr90a 8 cs1n t ac26 pr89b 8 csn c ae28 pr89a 8 d0 t ad27 pr88b 8 d1 c ad28 pr88a 8 d2 t ab24 pr87b 8 d3 c gnd gndio 4 ab23 pr87a 8 d4 t ab25 pr86b 8 d5 c ab26 pr86a 8 d6 t ac27 pr85b 8 d7 c lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-114 pinout information lattice semiconductor latticeecp2/m family data sheet ab27 pr85a 8 di/csspi0n t ad29 pr84b 8 dout/cson c ad30 pr84a 8 busy/sispi t aa25 pr83b 3 c gnd gndio 3 aa23 pr83a 3 t ac29 pr82b 3 c (lvds)* ac30 pr82a 3 t (lvds)* aa26 pr81b 3 c aa24 pr81a 3 t ab29 pr80b 3 c (lvds)* ab30 pr80a 3 rdqs80 t (lvds)* gnd gndio 3 y23 pr79b 3 c y25 pr79a 3 t aa27 pr78b 3 c (lvds)* aa28 pr78a 3 t (lvds)* y24 pr77b 3 rlm0_gpllc_fb_a c y26 pr77a 3 rlm0_gpllt_fb_a t aa29 pr76b 3 rlm0_gpllc_in_a** c (lvds)* aa30 pr76a 3 rlm0_gpllt_in_a** t (lvds)* r22 rlm0_pllcap 3 w 23 pr74b 3 rlm0_gdllc_fb_a c w 25 pr74a 3 rlm0_gdllt_fb_a t gnd gndio 3 y27 pr73b 3 rlm0_gdllc_in_a** c (lvds)* y28 pr73a 3 rlm0_gdllt_in_a** t (lvds)* w 24 pr72b 3 c w 26 pr72a 3 t y29 pr71b 3 c (lvds)* y30 pr71a 3 rdqs71 t (lvds)* v25 pr70b 3 c gnd gndio 3 v23 pr70a 3 t w 27 pr69b 3 c (lvds)* w 28 pr69a 3 t (lvds)* v26 pr68b 3 c v24 pr68a 3 t w 29 pr67b 3 c (lvds)* w 30 pr67a 3 t (lvds)* u25 pr66b 3 c gnd gndio 3 u23 pr66a 3 t v29 pr65b 3 c (lvds)* lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-115 pinout information lattice semiconductor latticeecp2/m family data sheet v30 pr65a 3 t (lvds)* u26 pr64b 3 c u24 pr64a 3 t u27 pr63b 3 c (lvds)* u28 pr63a 3 rdqs63 t (lvds)* gnd gndio 3 t23 pr62b 3 c t25 pr62a 3 t u29 pr61b 3 c (lvds)* u30 pr61a 3 t (lvds)* t24 pr60b 3 vref2_3 c t26 pr60a 3 vref1_3 t t27 pr59b 3 pclkc3_0 c (lvds)* t28 pr59a 3 pclkt3_0 t (lvds)* r24 pr57b 2 pclkc2_0 c r26 pr57a 2 pclkt2_0 t gnd gndio 2 t29 pr56b 2 c (lvds)* t30 pr56a 2 t (lvds)* r23 pr55b 2 c r25 pr55a 2 t r27 pr54b 2 c (lvds)* r28 pr54a 2 rdqs54 t (lvds)* p26 pr53b 2 c gnd gndio 2 p24 pr53a 2 t r29 pr52b 2 c (lvds)* r30 pr52a 2 t (lvds)* p25 pr51b 2 c p23 pr51a 2 t p27 pr50b 2 c (lvds)* p28 pr50a 2 t (lvds)* gnd gndio 2 n24 pr39b 2 rum0_spllc_fb_a c n26 pr39a 2 rum0_spllt_fb_a t n23 pr38b 2 rum0_spllc_in_a c n25 pr38a 2 rum0_spllt_in_a t p29 pr37b 2 c (lvds)* p30 pr37a 2 rdqs37 t (lvds)* m26 pr36b 2 c gnd gndio 2 m24 pr36a 2 t n29 pr35b 2 c (lvds)* n30 pr35a 2 t (lvds)* lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-116 pinout information lattice semiconductor latticeecp2/m family data sheet m25 pr34b 2 c m23 pr34a 2 t m27 pr33b 2 c (lvds)* m28 pr33a 2 t (lvds)* l26 pr32b 2 c gnd gndio 2 l24 pr32a 2 t m29 pr31b 2 c (lvds)* m30 pr31a 2 t (lvds)* l25 pr30b 2 c l23 pr30a 2 t l27 pr29b 2 c (lvds)* l28 pr29a 2 rdqs29 t (lvds)* gnd gndio 2 k24 pr28b 2 c k26 pr28a 2 t l29 pr27b 2 c (lvds)* l30 pr27a 2 t (lvds)* k23 pr26b 2 c k25 pr26a 2 t k27 pr25b 2 c (lvds)* k28 pr25a 2 t (lvds)* j24 pr24b 2 c j26 pr24a 2 t gnd gndio 2 k29 pr23b 2 c (lvds)* k30 pr23a 2 t (lvds)* j23 pr22b 2 c j25 pr22a 2 t j27 pr21b 2 c (lvds)* j28 pr21a 2 rdqs21 t (lvds)* h26 pr20b 2 c gnd gndio 2 h24 pr20a 2 t j29 pr19b 2 c (lvds)* j30 pr19a 2 t (lvds)* h25 pr18b 2 c h23 pr18a 2 t g27 pr15b 2 rum1_spllc_fb_a c gnd gndio 2 h27 pr15a 2 rum1_spllt_fb_a t g29 pr14b 2 rum1_spllc_in_a c (lvds)* g28 pr14a 2 rum1_spllt_in_a t (lvds)* gnd gndio 2 lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-117 pinout information lattice semiconductor latticeecp2/m family data sheet g26 pr6b 2 c (lvds)* g25 pr6a 2 t (lvds)* g30 pr5b 2 c f30 pr5a 2 t f26 pr4b 2 c (lvds)* f27 pr4a 2 t (lvds)* f29 pr3b 2 c gnd gndio 2 f28 pr3a 2 t h29 pr2b 2 vref2_2 c (lvds)* h30 pr2a 2 vref1_2 t (lvds)* b26 pt100b 1 vref2_1 c a26 pt100a 1 vref1_1 t gnd gndio 1 c25 pt99b 1 c d25 pt99a 1 t j22 pt98b 1 c j21 pt98a 1 t b25 pt97b 1 c a25 pt97a 1 t e24 pt96b 1 c f24 pt96a 1 t gnd gndio 1 f23 pt95b 1 c h22 pt95a 1 t d24 pt94b 1 c c24 pt94a 1 t e23 pt93b 1 c g23 pt93a 1 t b24 pt92b 1 c a24 pt92a 1 t c27 pt91b 1 c gnd gndio 1 d27 pt91a 1 t c26 pt90b 1 c d26 pt90a 1 t a27 pt89b 1 c b27 pt89a 1 t a28 pt88b 1 c b28 pt88a 1 t a29 pt87b 1 c b29 pt87a 1 t gnd gndio 1 h21 pt80b 1 c lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-118 pinout information lattice semiconductor latticeecp2/m family data sheet f22 pt80a 1 t b23 pt79b 1 c a23 pt79a 1 t g24 pt78b 1 c e22 pt78a 1 t gnd gndio 1 d22 pt77b 1 c c22 pt77a 1 t g22 pt76b 1 c e21 pt76a 1 t b22 pt75b 1 c a22 pt75a 1 t h20 pt74b 1 c f21 pt74a 1 t f20 pt73b 1 c gnd gndio 1 h19 pt73a 1 t d21 pt72b 1 c c21 pt72a 1 t e20 pt71b 1 c g21 pt71a 1 t b21 pt70b 1 c a21 pt70a 1 t f19 pt69b 1 c g20 pt69a 1 t e19 pt68b 1 c gnd gndio 1 g19 pt68a 1 t d20 pt67b 1 c c20 pt67a 1 t b20 pt66b 1 c a20 pt66a 1 t f18 pt65b 1 c h18 pt65a 1 t d19 pt64b 1 c c19 pt64a 1 t gnd gndio 1 g18 pt63b 1 c e18 pt63a 1 t h17 pt62b 1 c f17 pt62a 1 t g17 pt61b 1 c e17 pt61a 1 t b19 pt60b 1 c lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-119 pinout information lattice semiconductor latticeecp2/m family data sheet a19 pt60a 1 t gnd gndio 1 d17 pt59b 1 c b18 pt59a 1 t c17 pt58b 1 c a18 pt58a 1 t h16 pt57b 1 pclkc1_0 c f16 pt57a 1 pclkt1_0 t k16 xres 1 e16 pt55b 0 pclkc0_0 c gnd gndio 0 g16 pt55a 0 pclkt0_0 t b17 pt54b 0 c a17 pt54a 0 t j15 pt53b 0 c j16 pt53a 0 t c16 pt52b 0 c d16 pt52a 0 t f15 pt51b 0 c h15 pt51a 0 t e15 pt50b 0 c gnd gndio 0 g15 pt50a 0 t c15 pt49b 0 c d15 pt49a 0 t b16 pt48b 0 c a16 pt48a 0 t e14 pt47b 0 c g14 pt47a 0 t b15 pt46b 0 c a15 pt46a 0 t gnd gndio 0 h14 pt45b 0 c f14 pt45a 0 t d14 pt44b 0 c c14 pt44a 0 t g13 pt43b 0 c e13 pt43a 0 t b14 pt42b 0 c a14 pt42a 0 t gnd gndio 0 h13 pt41b 0 c f13 pt41a 0 t g12 pt40b 0 c lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-120 pinout information lattice semiconductor latticeecp2/m family data sheet e12 pt40a 0 t b13 pt39b 0 c a13 pt39a 0 t h12 pt38b 0 c f12 pt38a 0 t c12 pt37b 0 c gnd gndio 0 d12 pt37a 0 t b12 pt36b 0 c a12 pt36a 0 t e11 pt35b 0 c g11 pt35a 0 t f11 pt34b 0 c h11 pt34a 0 t c11 pt33b 0 c d11 pt33a 0 t b11 pt32b 0 c gnd gndio 0 a11 pt32a 0 t e10 pt31b 0 c g10 pt31a 0 t f10 pt30b 0 c h10 pt30a 0 t d10 pt29b 0 c c10 pt29a 0 t gnd gndio 0 a7 pt16b 0 c b7 pt16a 0 t a6 pt15b 0 c b6 pt15a 0 t c7 pt14b 0 c gnd gndio 0 d7 pt14a 0 t d8 pt13b 0 c e7 pt13a 0 t c6 pt12b 0 c d6 pt12a 0 t c5 pt11b 0 c d5 pt11a 0 t e9 pt10b 0 c g9 pt10a 0 t gnd gndio 0 b10 pt9b 0 c a10 pt9a 0 t lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-121 pinout information lattice semiconductor latticeecp2/m family data sheet d9 pt8b 0 c c9 pt8a 0 t f9 pt7b 0 c h9 pt7a 0 t b9 pt6b 0 c a9 pt6a 0 t gnd gndio 0 e8 pt5b 0 c g8 pt5a 0 t a8 pt4b 0 c b8 pt4a 0 t f8 pt3b 0 c f7 pt3a 0 t j10 pt2b 0 vref2_0 c j9 pt2a 0 vref1_0 t aa11 vcc - aa20 vcc - k11 vcc - k21 vcc - k22 vcc - l11 vcc - l12 vcc - l13 vcc - l18 vcc - l19 vcc - l20 vcc - m11 vcc - m20 vcc - n11 vcc - n20 vcc - v11 vcc - v20 vcc - w 11 vcc - w 20 vcc - y10 vcc - y11 vcc - y12 vcc - y13 vcc - y18 vcc - y19 vcc - y20 vcc - j13 vccio0 0 j14 vccio0 0 k12 vccio0 0 lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-122 pinout information lattice semiconductor latticeecp2/m family data sheet k13 vccio0 0 k14 vccio0 0 k15 vccio0 0 j17 vccio1 1 j18 vccio1 1 j20 vccio1 1 k17 vccio1 1 k18 vccio1 1 k20 vccio1 1 l21 vccio2 2 m21 vccio2 2 m22 vccio2 2 n21 vccio2 2 n22 vccio2 2 r21 vccio2 2 u21 vccio3 3 u22 vccio3 3 v21 vccio3 3 v22 vccio3 3 w 21 vccio3 3 y22 vccio3 3 aa16 vccio4 4 aa17 vccio4 4 aa18 vccio4 4 aa19 vccio4 4 ab17 vccio4 4 ab18 vccio4 4 aa12 vccio5 5 aa13 vccio5 5 aa14 vccio5 5 ab12 vccio5 5 ab13 vccio5 5 ab14 vccio5 5 u10 vccio6 6 u9 vccio6 6 v10 vccio6 6 w 10 vccio6 6 w 9 vccio6 6 y9 vccio6 6 l10 vccio7 7 l9 vccio7 7 m10 vccio7 7 n10 vccio7 7 p10 vccio7 7 lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-123 pinout information lattice semiconductor latticeecp2/m family data sheet r10 vccio7 7 aa21 vccio8 8 y21 vccio8 8 aa15 vccaux - ab11 vccaux - ab19 vccaux - ab20 vccaux - j11 vccaux - j12 vccaux - j19 vccaux - k19 vccaux - l22 vccaux - m9 vccaux - n9 vccaux - p21 vccaux - p9 vccaux - t10 vccaux - t21 vccaux - v9 vccaux - w 22 vccaux - a1 gnd - a30 gnd - ac28 gnd - ac3 gnd - ah13 gnd - ah18 gnd - ah23 gnd - ah28 gnd - ah3 gnd - ah8 gnd - ak1 gnd - ak30 gnd - c13 gnd - c18 gnd - c23 gnd - c28 gnd - c3 gnd - c8 gnd - h28 gnd - h3 gnd - l14 gnd - l15 gnd - l16 gnd - l17 gnd - lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-124 pinout information lattice semiconductor latticeecp2/m family data sheet m12 gnd - m13 gnd - m14 gnd - m15 gnd - m16 gnd - m17 gnd - m18 gnd - m19 gnd - n12 gnd - n13 gnd - n14 gnd - n15 gnd - n16 gnd - n17 gnd - n18 gnd - n19 gnd - n28 gnd - n3 gnd - p11 gnd - p12 gnd - p13 gnd - p14 gnd - p15 gnd - p16 gnd - p17 gnd - p18 gnd - p19 gnd - p20 gnd - r11 gnd - r12 gnd - r13 gnd - r14 gnd - r15 gnd - r16 gnd - r17 gnd - r18 gnd - r19 gnd - r20 gnd - t11 gnd - t12 gnd - t13 gnd - t14 gnd - t15 gnd - t16 gnd - lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-125 pinout information lattice semiconductor latticeecp2/m family data sheet t17 gnd - t18 gnd - t19 gnd - t20 gnd - u11 gnd - u12 gnd - u13 gnd - u14 gnd - u15 gnd - u16 gnd - u17 gnd - u18 gnd - u19 gnd - u20 gnd - v12 gnd - v13 gnd - v14 gnd - v15 gnd - v16 gnd - v17 gnd - v18 gnd - v19 gnd - v28 gnd - v3 gnd - w 12 gnd - w 13 gnd - w 14 gnd - w 15 gnd - w 16 gnd - w 17 gnd - w 18 gnd - w 19 gnd - y14 gnd - y15 gnd - y16 gnd - y17 gnd - a2 nc - a3 nc - a4 nc - a5 nc - ab28 nc - ac4 nc - ad23 nc - ae1 nc - lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-126 pinout information lattice semiconductor latticeecp2/m family data sheet ae2 nc - ae29 nc - ae3 nc - ae30 nc - ae4 nc - ae5 nc - ae6 nc - af1 nc - af2 nc - af23 nc - af26 nc - af27 nc - af28 nc - af29 nc - af3 nc - af30 nc - af4 nc - af5 nc - ag1 nc - ag13 nc - ag16 nc - ag18 nc - ag2 nc - ag26 nc - ag27 nc - ag28 nc - ag29 nc - ag3 nc - ag30 nc - ag4 nc - ag8 nc - ah1 nc - ah16 nc - ah2 nc - ah26 nc - ah27 nc - ah29 nc - ah30 nc - ah4 nc - aj1 nc - aj2 nc - aj27 nc - aj28 nc - aj29 nc - lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-127 pinout information lattice semiconductor latticeecp2/m family data sheet aj3 nc - aj30 nc - ak2 nc - ak27 nc - ak28 nc - ak29 nc - ak3 nc - b1 nc - b2 nc - b3 nc - b30 nc - b4 nc - b5 nc - c1 nc - c2 nc - c29 nc - c30 nc - c4 nc - d13 nc - d18 nc - d23 nc - d28 nc - d29 nc - d3 nc - d30 nc - d4 nc - e25 nc - e26 nc - e27 nc - e28 nc - e29 nc - e3 nc - e30 nc - e4 nc - e5 nc - e6 nc - f25 nc - f5 nc - f6 nc - g6 nc - g7 nc - k10 nc - k9 nc - n27 nc - lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-128 pinout information lattice semiconductor latticeecp2/m family data sheet n4 nc - r1 nc - r2 nc - v27 nc - v4 nc - p22 vccpll - p8 vccpll - t22 vccpll - y7 vccpll - * supports true lvds. other differential signals must be emulated with external resistors. ** these dedicated input pins can be used for gplls or gdlls within the respective quadrant. lfe2-70e/70se logic signal connections: 900 fpbga (cont.) ball number ball function bank dual function differential
4-129 pinout information lattice semiconductor latticeecp2/m family data sheet lfe2m20e/20se and lfe2m35e/35se logic signal connections: 256 fpbga lfe2m20e/20se lfe2m35e/35se ball number ball function bank dual function differential ball function bank dual function differential a2 pl2a 7 t (lvds)* pl2a 7 t (lvds)* b2 pl2b 7 c (lvds)* pl2b 7 c(lvds)* d3 pl3a 7 t pl3a 7 t c2 pl3b 7 c pl3b 7 c e4 pl4a 7 t (lvds)* pl4a 7 t (lvds)* vccio vccio7 7 vccio7 7 e5 pl4b 7 c (lvds)* pl4b 7 c(lvds)* b1 pl5a 7 t pl5a 7 t c1 pl5b 7 c pl5b 7 c d2 pl6a 7 ldqs6 t (lvds)* pl6a 7 ldqs6 t (lvds)* gndio gndio7 7 gndio7 7 d1 pl6b 7 c (lvds)* pl6b 7 c(lvds)* e1 pl7a 7 t pl7a 7 t f1 pl7b 7 c pl7b 7 c vccio vccio7 7 vccio7 7 f3 pl8a 7 t (lvds)* pl8a 7 t (lvds)* f2 pl8b 7 c (lvds)* pl8b 7 c(lvds)* f6 pl9a 7 vref2_7 t pl9a 7 vref2_7 t f5 pl9b 7 vref1_7 c pl9b 7 vref1_7 c gndio gndio7 7 gndio7 7 g4 pl11a 7 lum0_spllt_in_a t (lvds)* pl11a 7 lum0_spllt_in_a t (lvds)* g3 pl11b 7 lum0_spllc_in_a c (lvds)* pl11b 7 lum0_spllc_in_a c(lvds)* g1 pl12a 7 lum0_spllt_fb_a t pl12a 7 lum0_spllt_fb_a t g2 pl12b 7 lum0_spllc_fb_a c pl12b 7 lum0_spllc_fb_a c h1 pl13a 7 t (lvds)* pl13a 7 t (lvds)* vccio vccio7 7 vccio7 7 j1 pl13b 7 c (lvds)* pl13b 7 c(lvds)* h2 pl14a 7 t pl14a 7 t h3 pl14b 7 c pl14b 7 c gndio gndio7 7 gndio7 7 vccio vccio7 7 vccio7 7 g6 pl24a 7 t (lvds)* pl34a 7 t (lvds)* h6 pl24b 7 c (lvds)* pl34b 7 c(lvds)* j2 pl25a 7 pclkt7_0 t pl35a 7 pclkt7_0 t gndio gndio7 7 gndio7 7 k1 pl25b 7 pclkc7_0 c pl35b 7 pclkc7_0 c h4 pl27a 6 pclkt6_0 t (lvds)* pl37a 6 pclkt6_0 t (lvds)* h5 pl27b 6 pclkc6_0 c (lvds)* pl37b 6 pclkc6_0 c(lvds)* j4 pl28a 6 vref2_6 t pl38a 6 vref2_6 t k4 pl28b 6 vref1_6 c pl38b 6 vref1_6 c vccio vccio6 6 vccio6 6 j6 pl31a 6 llm1_spllt_in_a t (lvds)* pl41a 6 llm2_spllt_in_a t (lvds)* gndio gndio6 6 gndio6 6 j5 pl31b 6 llm1_spllc_in_a c (lvds)* pl41b 6 llm2_spllc_in_a c(lvds)* k3 pl32a 6 llm1_spllt_fb_a t pl42a 6 llm2_spllt_fb_a t k2 pl32b 6 llm1_spllc_fb_a c pl42b 6 llm2_spllc_fb_a c vccio vccio6 6 vccio6 6 gndio gndio6 6 gndio6 6
4-130 pinout information lattice semiconductor latticeecp2/m family data sheet l1 pl42a 6 llm0_gpllt_in_a t (lvds)* pl57a 6 llm0_gpllt_in_a**/ldqs57 t (lvds)* gndio gndio6 6 gndio6 6 l2 pl42b 6 llm0_gpllc_in_a c (lvds)* pl57b 6 llm0_gpllc_in_a** c(lvds)* l3 pl43a 6 llm0_gpllt_fb_a t pl58a 6 llm0_gpllt_fb_a t l4 pl43b 6 llm0_gpllc_fb_a c pl58b 6 llm0_gpllc_fb_a c vccio vccio6 6 vccio6 6 m1 pl44a 6 llm0_gdllt_in_a t (lvds)* pl59a 6 llm0_gdllt_in_a** t (lvds)* n1 pl44b 6 llm0_gdllc_in_a c (lvds)* pl59b 6 llm0_gdllc_in_a** c(lvds)* n2 pl45a 6 llm0_gdllt_fb_a t pl60a 6 llm0_gdllt_fb_a t n3 pl45b 6 llm0_gdllc_fb_a c pl60b 6 llm0_gdllc_fb_a c gndio gndio6 6 gndio6 6 m4 llm0_pllcap 6 llm0_pllcap 6 vccio vccio6 6 vccio6 6 gndio gndio6 6 gndio6 6 k6 tck - tck - l5 tdi - tdi - n4 tms - tms - n6 tdo - tdo - k7 vccj - vccj - m5 pb2a 5 t pb2a 5 t n5 pb2b 5 c pb2b 5 c l6 pb3a 5 t pb3a 5 t m6 pb3b 5 c pb3b 5 c p3 pb4a 5 t pb4a 5 t vccio vccio5 5 vccio5 5 p4 pb4b 5 c pb4b 5 c p2 pb5a 5 t pb5a 5 t p1 pb5b 5 c pb5b 5 c r1 pb6a 5 bdqs6 t pb6a 5 bdqs6 t gndio gndio5 5 gndio5 5 r2 pb6b 5 c pb6b 5 c r3 pb7a 5 t pb7a 5 t t2 pb7b 5 c pb7b 5 c r4 pb8a 5 t pb8a 5 t vccio vccio5 5 vccio5 5 t3 pb8b 5 c pb8b 5 c t4 pb10a 5 t pb10a 5 t gndio gndio5 5 gndio5 5 t5 pb10b 5 c pb10b 5 c vccio vccio5 5 vccio5 5 gndio gndio5 5 gndio5 5 t6 pb16a 5 vref2_5 t pb34a 5 vref2_5 t r6 pb16b 5 vref1_5 c pb34b 5 vref1_5 c p6 pb17a 5 pclkt5_0 t pb35a 5 pclkt5_0 t p7 pb17b 5 pclkc5_0 c pb35b 5 pclkc5_0 c vccio vccio5 5 vccio5 5 gndio gndio5 5 gndio5 5 t7 pb22a 4 pclkt4_0 t pb40a 4 pclkt4_0 t lfe2m20e/20se and lfe2m35e/35se logic signal connections: 256 fpbga (cont.) lfe2m20e/20se lfe2m35e/35se ball number ball function bank dual function differential ball function bank dual function differential
4-131 pinout information lattice semiconductor latticeecp2/m family data sheet vccio vccio4 4 vccio4 4 t8 pb22b 4 pclkc4_0 c pb40b 4 pclkc4_0 c l7 pb23a 4 vref2_4 t pb41a 4 vref2_4 t l8 pb23b 4 vref1_4 c pb41b 4 vref1_4 c gndio gndio4 4 gndio4 4 vccio vccio4 4 vccio4 4 gndio gndio4 4 gndio4 4 p8 pb29a 4 t pb47a 4 t n8 pb29b 4 c pb47b 4 c r7 pb30a 4 t pb48a 4 t r8 pb30b 4 c pb48b 4 c n7 pb31a 4 t pb49a 4 t m8 pb31b 4 c pb49b 4 c vccio vccio4 4 vccio4 4 r9 pb32a 4 t pb50a 4 t t9 pb32b 4 c pb50b 4 c gndio gndio4 4 gndio4 4 t10 pb33a 4 bdqs33 t pb51a 4 bdqs51 t r10 pb33b 4 c pb51b 4 c n9 pb34a 4 t pb52a 4 t p10 pb34b 4 c pb52b 4 c vccio vccio4 4 vccio4 4 gndio gndio4 4 gndio4 4 l9 pb47a 4 t pb65a 4 t m9 pb47b 4 c pb65b 4 c t11 pb49a 4 t pb67a 4 t r11 pb49b 4 c pb67b 4 c vccio vccio4 4 vccio4 4 t12 pb50a 4 t pb68a 4 t t13 pb50b 4 c pb68b 4 c gndio gndio4 4 gndio4 4 p11 pb51a 4 bdqs51 t pb69a 4 bdqs69 t n10 pb51b 4 c pb69b 4 c t14 pb52a 4 t pb70a 4 t r13 pb52b 4 c pb70b 4 c r15 pb53a 4 t pb71a 4 t r16 pb53b 4 c pb71b 4 c vccio vccio4 4 vccio4 4 r14 pb54a 4 t pb72a 4 t p15 pb54b 4 c pb72b 4 c p16 pb55a 4 t pb73a 4 t p14 pb55b 4 c pb73b 4 c gndio gndio4 4 gndio4 4 l11 cfg2 8 cfg2 8 l10 cfg1 8 cfg1 8 p13 cfg0 8 cfg0 8 n12 programn 8 programn 8 n11 cclk 8 cclk 8 lfe2m20e/20se and lfe2m35e/35se logic signal connections: 256 fpbga (cont.) lfe2m20e/20se lfe2m35e/35se ball number ball function bank dual function differential ball function bank dual function differential
4-132 pinout information lattice semiconductor latticeecp2/m family data sheet m11 initn 8 initn 8 n13 done 8 done 8 gndio gndio8 8 gndio8 8 m12 pr53b 8 w riten c pr68b 8 w riten c m13 pr53a 8 cs1n t pr68a 8 cs1n t n14 pr52b 8 csn c pr67b 8 csn c n15 pr52a 8 d0 t pr67a 8 d0 t vccio vccio8 8 vccio8 8 n16 pr51b 8 d1 c pr66b 8 d1 c m16 pr51a 8 d2 t pr66a 8 d2 t l12 pr50b 8 d3 c pr65b 8 d3 c gndio gndio8 8 gndio8 8 l13 pr50a 8 d4 t pr65a 8 d4 t l16 pr49b 8 d5 c pr64b 8 d5 c k16 pr49a 8 d6 t pr64a 8 d6 t l14 pr48b 8 d7 c pr63b 8 d7 c vccio vccio8 8 vccio8 8 l15 pr48a 8 di t pr63a 8 di t k13 pr47b 8 dout_cson c pr62b 8 dout_cson c k14 pr47a 8 busy t pr62a 8 busy t k11 rlm0_pllcap 3 rlm0_pllcap 3 k15 pr45b 3 rlm0_gdllc_fb_a c pr60b 3 rlm0_gdllc_fb_a c gndio gndio3 3 gndio3 3 j16 pr45a 3 rlm0_gdllt_fb_a t pr60a 3 rlm0_gdllt_fb_a t h16 pr44b 3 rlm0_gdllc_in_a c (lvds)* pr59b 3 rlm0_gdllc_in_a** c(lvds)* j15 pr44a 3 rlm0_gdllt_in_a t (lvds)* pr59a 3 rlm0_gdllt_in_a** t (lvds)* j14 pr43b 3 rlm0_gpllc_in_a c pr58b 3 rlm0_gpllc_in_a** c vccio vccio3 3 vccio3 3 j13 pr43a 3 rlm0_gpllt_in_a t pr58a 3 rlm0_gpllt_in_a** t h13 pr42b 3 rlm0_gpllc_fb_a c (lvds)* pr57b 3 rlm0_gpllc_fb_a c(lvds)* h12 pr42a 3 rlm0_gpllt_fb_a t (lvds)* pr57a 3 rlm0_gpllt_fb_a/rdqs57 t (lvds)* gndio gndio3 3 gndio3 3 vccio vccio3 3 vccio3 3 g16 pr32b 3 rlm1_spllc_fb_a c pr42b 3 rlm2_spllc_fb_a c vccio vccio3 3 vccio3 3 h15 pr32a 3 rlm1_spllt_fb_a t pr42a 3 rlm2_spllt_fb_a t e16 pr31b 3 rlm1_spllc_in_a c (lvds)* pr41b 3 rlm2_spllc_in_a c(lvds)* f15 pr31a 3 rlm1_spllt_in_a t (lvds)* pr41a 3 rlm2_spllt_in_a t (lvds)* gndio gndio3 3 gndio3 3 vccio vccio3 3 vccio3 3 f16 pr28b 3 vref2_3 c pr38b 3 vref2_3 c g15 pr28a 3 vref1_3 t pr38a 3 vref1_3 t j11 pr27b 3 pclkc3_0 c (lvds)* pr37b 3 pclkc3_0 c(lvds)* j12 pr27a 3 pclkt3_0 t (lvds)* pr37a 3 pclkt3_0 t (lvds)* g14 pr25b 2 pclkc2_0 c pr35b 2 pclkc2_0 c g13 pr25a 2 pclkt2_0 t pr35a 2 pclkt2_0 t gndio gndio2 2 gndio2 2 f14 pr24b 2 c (lvds)* pr34b 2 c(lvds)* lfe2m20e/20se and lfe2m35e/35se logic signal connections: 256 fpbga (cont.) lfe2m20e/20se lfe2m35e/35se ball number ball function bank dual function differential ball function bank dual function differential
4-133 pinout information lattice semiconductor latticeecp2/m family data sheet f13 pr24a 2 t (lvds)* pr34a 2 t (lvds)* vccio vccio2 2 vccio2 2 gndio gndio2 2 gndio2 2 h11 pr14b 2 c pr14b 2 c g11 pr14a 2 t pr14a 2 t e13 pr13b 2 c (lvds)* pr13b 2 c(lvds)* f12 pr13a 2 t (lvds)* pr13a 2 t (lvds)* vccio vccio2 2 vccio2 2 f11 pr12b 2 rum0_spllc_fb_a c pr12b 2 rum0_spllc_fb_a c e12 pr12a 2 rum0_spllt_fb_a t pr12a 2 rum0_spllt_fb_a t d16 pr11b 2 rum0_spllc_in_a c (lvds)* pr11b 2 rum0_spllc_in_a c(lvds)* d15 pr11a 2 rum0_spllt_in_a t (lvds)* pr11a 2 rum0_spllt_in_a t (lvds)* c16 pr9b 2 vref2_2 c pr9b 2 vref2_2 c gndio gndio2 2 gndio2 2 b16 pr9a 2 vref1_2 t pr9a 2 vref1_2 t vccio vccio2 2 vccio2 2 f4 xres - xres - c15 urc_sq_vccrx0 12 urc_sq_vccrx0 12 a14 urc_sq_hdinp0 12 t urc_sq_hdinp0 12 t b15 urc_sq_vccib0 12 urc_sq_vccib0 12 b14 urc_sq_hdinn0 12 c urc_sq_hdinn0 12 c c12 urc_sq_vcctx0 12 urc_sq_vcctx0 12 a11 urc_sq_hdoutp0 12 t urc_sq_hdoutp0 12 t a12 urc_sq_vccob0 12 urc_sq_vccob0 12 b11 urc_sq_hdoutn0 12 c urc_sq_hdoutn0 12 c c11 urc_sq_vcctx1 12 urc_sq_vcctx1 12 b10 urc_sq_hdoutn1 12 c urc_sq_hdoutn1 12 c c10 urc_sq_vccob1 12 urc_sq_vccob1 12 a10 urc_sq_hdoutp1 12 t urc_sq_hdoutp1 12 t c14 urc_sq_vccrx1 12 urc_sq_vccrx1 12 b13 urc_sq_hdinn1 12 c urc_sq_hdinn1 12 c c13 urc_sq_vccib1 12 urc_sq_vccib1 12 a13 urc_sq_hdinp1 12 t urc_sq_hdinp1 12 t b9 urc_sq_vccaux33 12 urc_sq_vccaux33 12 d8 urc_sq_refclkn 12 c urc_sq_refclkn 12 c d9 urc_sq_refclkp 12 t urc_sq_refclkp 12 t c9 urc_sq_vccp 12 urc_sq_vccp 12 a5 urc_sq_hdinp2 12 t urc_sq_hdinp2 12 t c5 urc_sq_vccib2 12 urc_sq_vccib2 12 b5 urc_sq_hdinn2 12 c urc_sq_hdinn2 12 c c4 urc_sq_vccrx2 12 urc_sq_vccrx2 12 a8 urc_sq_hdoutp2 12 t urc_sq_hdoutp2 12 t c8 urc_sq_vccob2 12 urc_sq_vccob2 12 b8 urc_sq_hdoutn2 12 c urc_sq_hdoutn2 12 c c7 urc_sq_vcctx2 12 urc_sq_vcctx2 12 b7 urc_sq_hdoutn3 12 c urc_sq_hdoutn3 12 c a6 urc_sq_vccob3 12 urc_sq_vccob3 12 a7 urc_sq_hdoutp3 12 t urc_sq_hdoutp3 12 t lfe2m20e/20se and lfe2m35e/35se logic signal connections: 256 fpbga (cont.) lfe2m20e/20se lfe2m35e/35se ball number ball function bank dual function differential ball function bank dual function differential
4-134 pinout information lattice semiconductor latticeecp2/m family data sheet c6 urc_sq_vcctx3 12 urc_sq_vcctx3 12 b4 urc_sq_hdinn3 12 c urc_sq_hdinn3 12 c b3 urc_sq_vccib3 12 urc_sq_vccib3 12 a4 urc_sq_hdinp3 12 t urc_sq_hdinp3 12 t c3 urc_sq_vccrx3 12 urc_sq_vccrx3 12 gndio gndio1 1 gndio1 1 vccio vccio1 1 vccio1 1 gndio gndio0 0 gndio0 0 vccio vccio0 0 vccio0 0 g10 vccpll - vccpll - g7 vcc - vcc - g9 vcc - vcc - h7 vcc - vcc - j10 vcc - vcc - k10 vcc - vcc - k8 vcc - vcc - e7 vccio0 0 vccio0 0 vccio vccio0 0 vccio0 0 e10 vccio1 1 vccio1 1 vccio vccio1 1 vccio1 1 e14 vccio2 2 vccio2 2 g12 vccio2 2 vccio2 2 vccio vccio2 2 vccio2 2 k12 vccio3 3 vccio3 3 m14 vccio3 3 vccio3 3 vccio vccio3 3 vccio3 3 m10 vccio4 4 vccio4 4 p12 vccio4 4 vccio4 4 vccio vccio4 4 vccio4 4 m7 vccio5 5 vccio5 5 p5 vccio5 5 vccio5 5 vccio vccio5 5 vccio5 5 k5 vccio6 6 vccio6 6 m3 vccio6 6 vccio6 6 vccio vccio6 6 vccio6 6 e3 vccio7 7 vccio7 7 g5 vccio7 7 vccio7 7 vccio vccio7 7 vccio7 7 t15 vccio8 8 vccio8 8 vccio vccio8 8 vccio8 8 g8 vccaux - vccaux - h10 vccaux - vccaux - j7 vccaux - vccaux - k9 vccaux - vccaux - a1 gnd - gnd - a15 gnd - gnd - a16 gnd - gnd - a3 gnd - gnd - lfe2m20e/20se and lfe2m35e/35se logic signal connections: 256 fpbga (cont.) lfe2m20e/20se lfe2m35e/35se ball number ball function bank dual function differential ball function bank dual function differential
4-135 pinout information lattice semiconductor latticeecp2/m family data sheet a9 gnd - gnd - b12 gnd - gnd - b6 gnd - gnd - e15 gnd - gnd - e2 gnd - gnd - h14 gnd - gnd - h8 gnd - gnd - h9 gnd - gnd - j3 gnd - gnd - j8 gnd - gnd - j9 gnd - gnd - m15 gnd - gnd - m2 gnd - gnd - p9 gnd - gnd - r12 gnd - gnd - r5 gnd - gnd - t1 gnd - gnd - t16 gnd - gnd - d10 nc - nc - d11 nc - nc - d12 nc - nc - d13 nc - nc - d14 nc - nc - d4 nc - nc - d5 nc - nc - d6 nc - nc - d7 nc - nc - e11 nc - nc - e6 nc - nc - e8 nc - nc - e9 nc - nc - f10 nc - nc - f7 nc - nc - f8 nc - nc - f9 nc - nc - * supports true lvds. other differential signals must be emulated with external resistors. ** these dedicated input pins can be used for gplls or gdlls within the respective quadrant. lfe2m20e/20se and lfe2m35e/35se logic signal connections: 256 fpbga (cont.) lfe2m20e/20se lfe2m35e/35se ball number ball function bank dual function differential ball function bank dual function differential
4-136 pinout information lattice semiconductor latticeecp2/m family data sheet lfem20e/20se and lfe2m35e/35se logic signal connections: 484 fpbga lfe2m20e/20se lfe2m35e,/35se ball number ball function bank dual function differential ball function bank dual function differential d1 pl2a 7 t (lvds)* pl2a 7 t (lvds)* e1 pl2b 7 c (lvds)* pl2b 7 c (lvds)* f1 pl3a 7 t pl3a 7 t f2 pl3b 7 c pl3b 7 c f5 pl4a 7 t (lvds)* pl4a 7 t (lvds)* vccio vccio7 7 vccio7 7 g6 pl4b 7 c (lvds)* pl4b 7 c (lvds)* f4 pl5a 7 t pl5a 7 t f3 pl5b 7 c pl5b 7 c g1 pl6a 7 ldqs6 t (lvds)* pl6a 7 ldqs6 t (lvds)* gndio gndio7 7 gndio7 7 g2 pl6b 7 c (lvds)* pl6b 7 c (lvds)* h1 pl7a 7 t pl7a 7 t h2 pl7b 7 c pl7b 7 c vccio vccio7 7 vccio7 7 h7 pl8a 7 t (lvds)* pl8a 7 t (lvds)* h6 pl8b 7 c (lvds)* pl8b 7 c (lvds)* g3 pl9a 7 vref2_7 t pl9a 7 vref2_7 t h3 pl9b 7 vref1_7 c pl9b 7 vref1_7 c gndio gndio7 7 gndio7 7 h5 pl11a 7 lum0_spllt_in_a t (lvds)* pl11a 7 lum0_spllt_in_a t (lvds)* h4 pl11b 7 lum0_spllc_in_a c (lvds)* pl11b 7 lum0_spllc_in_a c (lvds)* j1 pl12a 7 lum0_spllt_fb_a t pl12a 7 lum0_spllt_fb_a t j2 pl12b 7 lum0_spllc_fb_a c pl12b 7 lum0_spllc_fb_a c j3 pl13a 7 t (lvds)* pl13a 7 t (lvds)* vccio vccio7 7 vccio7 7 j4 pl13b 7 c (lvds)* pl13b 7 c (lvds)* j7 pl14a 7 t pl14a 7 t j6 pl14b 7 c pl14b 7 c gndio gndio7 7 gndio7 7 vccio vccio7 7 vccio7 7 k1 pl18a 7 lum1_spllt_in_a t (lvds)* pl28a 7 lum1_spllt_in_a t (lvds)* k2 pl18b 7 lum1_spllc_in_a c (lvds)* pl28b 7 lum1_spllc_in_a c (lvds)* j5 pl19a 7 lum1_spllt_fb_a t pl29a 7 lum1_spllt_fb_a t k5 pl19b 7 lum1_spllc_fb_a c pl29b 7 lum1_spllc_fb_a c vccio vccio7 7 vccio7 7 k7 pl20a 7 t (lvds)* pl30a 7 t (lvds)* k6 pl20b 7 c (lvds)* pl30b 7 c (lvds)* l6 pl21a 7 t pl31a 7 t l7 pl21b 7 c pl31b 7 c gndio gndio7 7 gndio7 7 l1 pl22a 7 ldqs22 t (lvds)* pl32a 7 ldqs32 t (lvds)* l2 pl22b 7 c (lvds)* pl32b 7 c (lvds)* m7 pl23a 7 t pl33a 7 t vccio vccio7 7 vccio7 7 l5 pl23b 7 c pl33b 7 c l3 pl24a 7 t (lvds)* pl34a 7 t (lvds)* l4 pl24b 7 c (lvds)* pl34b 7 c (lvds)*
4-137 pinout information lattice semiconductor latticeecp2/m family data sheet m1 pl25a 7 pclkt7_0 t pl35a 7 pclkt7_0 t gndio gndio7 7 gndio7 7 m2 pl25b 7 pclkc7_0 c pl35b 7 pclkc7_0 c m6 pl27a 6 pclkt6_0 t (lvds)* pl37a 6 pclkt6_0 t (lvds)* m5 pl27b 6 pclkc6_0 c (lvds)* pl37b 6 pclkc6_0 c (lvds)* m3 pl28a 6 vref2_6 t pl38a 6 vref2_6 t m4 pl28b 6 vref1_6 c pl38b 6 vref1_6 c vccio vccio6 6 vccio6 6 n7 pl31a 6 llm1_spllt_in_a t (lvds)* pl41a 6 llm2_spllt_in_a t (lvds)* gndio gndio6 6 gndio6 6 n6 pl31b 6 llm1_spllc_in_a c (lvds)* pl41b 6 llm2_spllc_in_a c (lvds)* n1 pl32a 6 llm1_spllt_fb_a t pl42a 6 llm2_spllt_fb_a t n2 pl32b 6 llm1_spllc_fb_a c pl42b 6 llm2_spllc_fb_a c vccio vccio6 6 vccio6 6 gndio gndio6 6 gndio6 6 p6 pl38a 6 ldqs38 t (lvds)* pl48a 6 ldqs48 t (lvds)* n5 pl38b 6 c (lvds)* pl48b 6 c (lvds)* p1 pl39a 6 t pl49a 6 t vccio vccio6 6 vccio6 6 p2 pl39b 6 c pl49b 6 c p3 pl40a 6 t (lvds)* pl50a 6 t (lvds)* p4 pl40b 6 c (lvds)* pl50b 6 c (lvds)* p5 pl41a 6 t pl51a 6 t gndio gndio6 6 gndio6 6 p7 pl41b 6 c pl51b 6 c r1 pl42a 6 llm0_gpllt_in_a** t (lvds)* pl57a 6 llm0_gpllt_in_a**/ldqs57 t (lvds)* gndio gndio6 6 gndio6 6 r2 pl42b 6 llm0_gpllc_in_a** c (lvds)* pl57b 6 llm0_gpllc_in_a** c (lvds)* r3 pl43a 6 llm0_gpllt_fb_a t pl58a 6 llm0_gpllt_fb_a t r4 pl43b 6 llm0_gpllc_fb_a c pl58b 6 llm0_gpllc_fb_a c vccio vccio6 6 vccio6 6 r6 pl44a 6 llm0_gdllt_in_a** t (lvds)* pl59a 6 llm0_gdllt_in_a** t (lvds)* r5 pl44b 6 llm0_gdllc_in_a** c (lvds)* pl59b 6 llm0_gdllc_in_a** c (lvds)* t1 pl45a 6 llm0_gdllt_fb_a t pl60a 6 llm0_gdllt_fb_a t t2 pl45b 6 llm0_gdllc_fb_a c pl60b 6 llm0_gdllc_fb_a c gndio gndio6 6 gndio6 6 r7 llm0_pllcap 6 llm0_pllcap 6 t6 pl47a 6 t (lvds)* pl62a 6 t (lvds)* t7 pl47b 6 c (lvds)* pl62b 6 c (lvds)* u1 pl48a 6 t pl63a 6 t u2 pl48b 6 c pl63b 6 c vccio vccio6 6 vccio6 6 t3 pl49a 6 t (lvds)* pl64a 6 t (lvds)* u3 pl49b 6 c (lvds)* pl64b 6 c (lvds)* u6 pl50a 6 t nc - u5 pl50b 6 c pl65b 6 c gndio gndio6 6 gndio6 6 v5 pl51a 6 ldqs51 t (lvds)* pl66a 6 ldqs66 t (lvds)* lfem20e/20se and lfe2m35e/35se logic signal connections: 484 fpbga (cont.) lfe2m20e/20se lfe2m35e,/35se ball number ball function bank dual function differential ball function bank dual function differential
4-138 pinout information lattice semiconductor latticeecp2/m family data sheet u4 pl51b 6 c (lvds)* pl66b 6 c (lvds)* v1 pl52a 6 t pl67a 6 t vccio vccio6 6 vccio6 6 v3 pl52b 6 c pl67b 6 c w 1 pl53a 6 t (lvds)* pl68a 6 t (lvds)* y1 pl53b 6 c (lvds)* pl68b 6 c (lvds)* aa1 pl54a 6 t pl69a 6 t gndio gndio6 6 gndio6 6 aa2 pl54b 6 c pl69b 6 c v4 tck - tck - y2 tdi - tdi - y3 tms - tms - w 3 tdo - tdo - w 4 vccj - vccj - w 5 pb2a 5 t pb2a 5 t y4 pb2b 5 c pb2b 5 c w 6 pb3a 5 t pb3a 5 t v6 pb3b 5 c pb3b 5 c aa3 pb4a 5 t pb4a 5 t vccio vccio5 5 vccio5 5 ab2 pb4b 5 c pb4b 5 c t8 pb5a 5 t pb5a 5 t u7 pb5b 5 c pb5b 5 c u8 pb6a 5 bdqs6 t pb6a 5 bdqs6 t gndio gndio5 5 gndio5 5 t9 pb6b 5 c pb6b 5 c v8 pb7a 5 t pb7a 5 t w 8 pb7b 5 c pb7b 5 c y6 pb8a 5 t pb8a 5 t vccio vccio5 5 vccio5 5 y5 pb8b 5 c pb8b 5 c ab3 pb9a 5 t pb9a 5 t ab4 pb9b 5 c pb9b 5 c ab5 pb10a 5 t pb10a 5 t gndio gndio5 5 gndio5 5 aa6 pb10b 5 c pb10b 5 c v9 pb13a 5 t pb31a 5 t u9 pb13b 5 c pb31b 5 c vccio vccio5 5 vccio5 5 - - - gndio5 5 u10 pb14a 5 t pb32a 5 t t10 pb14b 5 c pb32b 5 c gndio gndio5 5 gndio5 5 w 9 pb15a 5 bdqs15 t pb33a 5 bdqs33 t y8 pb15b 5 c pb33b 5 c aa7 pb16a 5 vref2_5 t pb34a 5 vref2_5 t y7 pb16b 5 vref1_5 c pb34b 5 vref1_5 c ab6 pb17a 5 pclkt5_0 t pb35a 5 pclkt5_0 t lfem20e/20se and lfe2m35e/35se logic signal connections: 484 fpbga (cont.) lfe2m20e/20se lfe2m35e,/35se ball number ball function bank dual function differential ball function bank dual function differential
4-139 pinout information lattice semiconductor latticeecp2/m family data sheet ab7 pb17b 5 pclkc5_0 c pb35b 5 pclkc5_0 c vccio vccio5 5 vccio5 5 gndio gndio5 5 gndio5 5 aa8 pb22a 4 pclkt4_0 t pb40a 4 pclkt4_0 t vccio vccio4 4 vccio4 4 ab8 pb22b 4 pclkc4_0 c pb40b 4 pclkc4_0 c aa9 pb23a 4 vref2_4 t pb41a 4 vref2_4 t y9 pb23b 4 vref1_4 c pb41b 4 vref1_4 c ab9 pb24a 4 bdqs24 t pb42a 4 bdqs42 t gndio gndio4 4 gndio4 4 ab10 pb24b 4 c pb42b 4 c aa10 pb25a 4 t pb43a 4 t y11 pb25b 4 c pb43b 4 c vccio vccio4 4 vccio4 4 gndio gndio4 4 gndio4 4 v10 pb29a 4 t pb47a 4 t u11 pb29b 4 c pb47b 4 c v11 pb30a 4 t pb48a 4 t w 11 pb30b 4 c pb48b 4 c aa11 pb31a 4 t pb49a 4 t ab11 pb31b 4 c pb49b 4 c vccio vccio4 4 vccio4 4 t11 pb32a 4 t pb50a 4 t u12 pb32b 4 c pb50b 4 c gndio gndio4 4 gndio4 4 aa12 pb33a 4 bdqs33 t pb51a 4 bdqs51 t y12 pb33b 4 c pb51b 4 c v12 pb34a 4 t pb52a 4 t w 12 pb34b 4 c pb52b 4 c ab12 pb35a 4 t pb53a 4 t aa13 pb35b 4 c pb53b 4 c vccio vccio4 4 vccio4 4 t12 pb36a 4 t pb54a 4 t u13 pb36b 4 c pb54b 4 c v13 pb37a 4 t pb55a 4 t t13 pb37b 4 c pb55b 4 c gndio gndio4 4 gndio4 4 ab13 pb38a 4 t pb56a 4 t ab14 pb38b 4 c pb56b 4 c u14 pb39a 4 t pb57a 4 t t14 pb39b 4 c pb57b 4 c aa14 pb40a 4 t pb58a 4 t vccio vccio4 4 vccio4 4 y14 pb40b 4 c pb58b 4 c w 14 pb41a 4 t pb59a 4 t v14 pb41b 4 c pb59b 4 c ab15 pb42a 4 bdqs42 t pb60a 4 bdqs60 t gndio gndio4 4 gndio4 4 lfem20e/20se and lfe2m35e/35se logic signal connections: 484 fpbga (cont.) lfe2m20e/20se lfe2m35e,/35se ball number ball function bank dual function differential ball function bank dual function differential
4-140 pinout information lattice semiconductor latticeecp2/m family data sheet aa15 pb42b 4 c pb60b 4 c v15 pb43a 4 t pb61a 4 t u15 pb43b 4 c pb61b 4 c ab16 pb44a 4 t pb62a 4 t vccio vccio4 4 vccio4 4 aa16 pb44b 4 c pb62b 4 c ab17 pb45a 4 t pb63a 4 t aa17 pb45b 4 c pb63b 4 c y15 pb46a 4 t pb64a 4 t gndio gndio4 4 gndio4 4 w 15 pb46b 4 c pb64b 4 c ab20 pb47a 4 t pb65a 4 t ab21 pb47b 4 c pb65b 4 c aa21 pb48a 4 t pb66a 4 t aa20 pb48b 4 c pb66b 4 c ab19 pb49a 4 t pb67a 4 t ab18 pb49b 4 c pb67b 4 c vccio vccio4 4 vccio4 4 y22 pb50a 4 t pb68a 4 t y21 pb50b 4 c pb68b 4 c gndio gndio4 4 gndio4 4 y17 pb51a 4 bdqs51 t pb69a 4 bdqs69 t y18 pb51b 4 c pb69b 4 c y16 pb52a 4 t pb70a 4 t w 17 pb52b 4 c pb70b 4 c y19 pb53a 4 t pb71a 4 t y20 pb53b 4 c pb71b 4 c vccio vccio4 4 vccio4 4 w 19 pb54a 4 t pb72a 4 t w 18 pb54b 4 c pb72b 4 c v17 pb55a 4 t pb73a 4 t v18 pb55b 4 c pb73b 4 c gndio gndio4 4 gndio4 4 w 20 cfg2 8 cfg2 8 v20 cfg1 8 cfg1 8 v19 cfg0 8 cfg0 8 v22 programn 8 programn 8 w 22 cclk 8 cclk 8 u18 initn 8 initn 8 u22 done 8 done 8 gndio gndio8 8 gndio8 8 u20 pr53b 8 w riten c pr68b 8 w riten c u21 pr53a 8 cs1n t pr68a 8 cs1n t u17 pr52b 8 csn c pr67b 8 csn c u16 pr52a 8 d0 t pr67a 8 d0 t vccio vccio8 8 vccio8 8 t16 pr51b 8 d1 c pr66b 8 d1 c t17 pr51a 8 d2 t pr66a 8 d2 t lfem20e/20se and lfe2m35e/35se logic signal connections: 484 fpbga (cont.) lfe2m20e/20se lfe2m35e,/35se ball number ball function bank dual function differential ball function bank dual function differential
4-141 pinout information lattice semiconductor latticeecp2/m family data sheet t22 pr50b 8 d3 c pr65b 8 d3 c gndio gndio8 8 gndio8 8 r22 pr50a 8 d4 t pr65a 8 d4 t t15 pr49b 8 d5 c pr64b 8 d5 c r17 pr49a 8 d6 t pr64a 8 d6 t t20 pr48b 8 d7 c pr63b 8 d7 c vccio vccio8 8 vccio8 8 t21 pr48a 8 di t pr63a 8 di t r21 pr47b 8 dout_cson c pr62b 8 dout_cson c r20 pr47a 8 busy t pr62a 8 busy t r16 rlm0_pllcap 3 rlm0_pllcap 3 r18 pr45b 3 rlm0_gdllc_fb_a c pr60b 3 rlm0_gdllc_fb_a c gndio gndio3 3 gndio3 3 r19 pr45a 3 rlm0_gdllt_fb_a t pr60a 3 rlm0_gdllt_fb_a t p22 pr44b 3 rlm0_gdllc_in_a** c (lvds)* pr59b 3 rlm0_gdllc_in_a** c (lvds)* p21 pr44a 3 rlm0_gdllt_in_a** t (lvds)* pr59a 3 rlm0_gdllt_in_a** t (lvds)* p16 pr43b 3 rlm0_gpllc_in_a** c pr58b 3 rlm0_gpllc_in_a** c vccio vccio3 3 vccio3 3 p17 pr43a 3 rlm0_gpllt_in_a** t pr58a 3 rlm0_gpllt_in_a** t p20 pr42b 3 rlm0_gpllc_fb_a c (lvds)* pr57b 3 rlm0_gpllc_fb_a c (lvds)* p19 pr42a 3 rlm0_gpllt_fb_a t (lvds)* pr57a 3 rlm0_gpllt_fb_a/rdqs57 t (lvds)* gndio gndio3 3 gndio3 3 - - - vccio3 3 p18 pr41b 3 c pr51b 3 c n16 pr41a 3 t pr51a 3 t gndio gndio3 3 gndio3 3 n22 pr40b 3 c (lvds)* pr50b 3 c (lvds)* n21 pr40a 3 t (lvds)* pr50a 3 t (lvds)* n17 pr39b 3 c pr49b 3 c n18 pr39a 3 t pr49a 3 t vccio vccio3 3 vccio3 3 m22 pr38b 3 c (lvds)* pr48b 3 c (lvds)* m21 pr38a 3 rdqs38 t (lvds)* pr48a 3 rdqs48 t (lvds)* m16 pr37b 3 c pr47b 3 c gndio gndio3 3 gndio3 3 m17 pr37a 3 t pr47a 3 t m20 pr36b 3 c (lvds)* pr46b 3 c (lvds)* m19 pr36a 3 t (lvds)* pr46a 3 t (lvds)* m18 pr35b 3 c pr45b 3 c vccio vccio3 3 vccio3 3 l16 pr35a 3 t pr45a 3 t l22 pr34b 3 c (lvds)* pr44b 3 c (lvds)* l21 pr34a 3 t (lvds)* pr44a 3 t (lvds)* k22 pr32b 3 rlm1_spllc_fb_a c pr42b 3 rlm2_spllc_fb_a c vccio vccio3 3 vccio3 3 k21 pr32a 3 rlm1_spllt_fb_a t pr42a 3 rlm2_spllt_fb_a t l17 pr31b 3 rlm1_spllc_in_a c (lvds)* pr41b 3 rlm2_spllc_in_a c (lvds)* l18 pr31a 3 rlm1_spllt_in_a t (lvds)* pr41a 3 rlm2_spllt_in_a t (lvds)* lfem20e/20se and lfe2m35e/35se logic signal connections: 484 fpbga (cont.) lfe2m20e/20se lfe2m35e,/35se ball number ball function bank dual function differential ball function bank dual function differential
4-142 pinout information lattice semiconductor latticeecp2/m family data sheet gndio gndio3 3 gndio3 3 l20 pr30b 3 c pr40b 3 c l19 pr30a 3 t pr40a 3 t k16 pr29b 3 c (lvds)* pr39b 3 c (lvds)* k17 pr29a 3 t (lvds)* pr39a 3 t (lvds)* vccio vccio3 3 vccio3 3 j16 pr28b 3 vref2_3 c pr38b 3 vref2_3 c k18 pr28a 3 vref1_3 t pr38a 3 vref1_3 t j22 pr27b 3 pclkc3_0 c (lvds)* pr37b 3 pclkc3_0 c (lvds)* j21 pr27a 3 pclkt3_0 t (lvds)* pr37a 3 pclkt3_0 t (lvds)* h22 pr25b 2 pclkc2_0 c pr35b 2 pclkc2_0 c h21 pr25a 2 pclkt2_0 t pr35a 2 pclkt2_0 t gndio gndio2 2 gndio2 2 j17 pr24b 2 c (lvds)* pr34b 2 c (lvds)* j18 pr24a 2 t (lvds)* pr34a 2 t (lvds)* j20 pr23b 2 c pr33b 2 c j19 pr23a 2 t pr33a 2 t vccio vccio2 2 vccio2 2 h16 pr22b 2 c (lvds)* pr32b 2 c (lvds)* h17 pr22a 2 rdqs22 t (lvds)* pr32a 2 rdqs32 t (lvds)* g22 pr21b 2 c pr31b 2 c gndio gndio2 2 gndio2 2 g21 pr21a 2 t pr31a 2 t h20 pr20b 2 c (lvds)* pr30b 2 c (lvds)* h19 pr20a 2 t (lvds)* pr30a 2 t (lvds)* g16 pr19b 2 rum1_spllc_fb_a c pr29b 2 rum1_spllc_fb_a c vccio vccio2 2 vccio2 2 h18 pr19a 2 rum1_spllt_fb_a t pr29a 2 rum1_spllt_fb_a t f22 pr18b 2 rum1_spllc_in_a c (lvds)* pr28b 2 rum1_spllc_in_a c (lvds)* f21 pr18a 2 rum1_spllt_in_a t (lvds)* pr28a 2 rum1_spllt_in_a t (lvds)* gndio gndio2 2 - - g20 pr16b 2 c pr26b 2 c vccio vccio2 2 - - f20 pr16a 2 t pr26a 2 t - - - gndio2 2 g17 pr15b 2 c (lvds)* pr25b 2 c (lvds)* f17 pr15a 2 t (lvds)* pr25a 2 t (lvds)* - - - vccio2 2 gndio gndio2 2 gndio2 2 e22 pr14b 2 c pr14b 2 c d22 pr14a 2 t pr14a 2 t e20 pr13b 2 c (lvds)* pr13b 2 c (lvds)* d20 pr13a 2 t (lvds)* pr13a 2 t (lvds)* vccio vccio2 2 vccio2 2 d19 pr12b 2 rum0_spllc_fb_a c pr12b 2 rum0_spllc_fb_a c e19 pr12a 2 rum0_spllt_fb_a t pr12a 2 rum0_spllt_fb_a t f18 pr11b 2 rum0_spllc_in_a c (lvds)* pr11b 2 rum0_spllc_in_a c (lvds)* f19 pr11a 2 rum0_spllt_in_a t (lvds)* pr11a 2 rum0_spllt_in_a t (lvds)* lfem20e/20se and lfe2m35e/35se logic signal connections: 484 fpbga (cont.) lfe2m20e/20se lfe2m35e,/35se ball number ball function bank dual function differential ball function bank dual function differential
4-143 pinout information lattice semiconductor latticeecp2/m family data sheet e18 pr9b 2 vref2_2 c pr9b 2 vref2_2 c gndio gndio2 2 gndio2 2 d18 pr9a 2 vref1_2 t pr9a 2 vref1_2 t vccio vccio2 2 - - f16 xres - xres - c22 urc_sq_vccrx0 12 urc_sq_vccrx0 12 a21 urc_sq_hdinp0 12 t urc_sq_hdinp0 12 t b22 urc_sq_vccib0 12 urc_sq_vccib0 12 b21 urc_sq_hdinn0 12 c urc_sq_hdinn0 12 c c19 urc_sq_vcctx0 12 urc_sq_vcctx0 12 a18 urc_sq_hdoutp0 12 t urc_sq_hdoutp0 12 t a19 urc_sq_vccob0 12 urc_sq_vccob0 12 b18 urc_sq_hdoutn0 12 c urc_sq_hdoutn0 12 c c18 urc_sq_vcctx1 12 urc_sq_vcctx1 12 b17 urc_sq_hdoutn1 12 c urc_sq_hdoutn1 12 c c17 urc_sq_vccob1 12 urc_sq_vccob1 12 a17 urc_sq_hdoutp1 12 t urc_sq_hdoutp1 12 t c21 urc_sq_vccrx1 12 urc_sq_vccrx1 12 b20 urc_sq_hdinn1 12 c urc_sq_hdinn1 12 c c20 urc_sq_vccib1 12 urc_sq_vccib1 12 a20 urc_sq_hdinp1 12 t urc_sq_hdinp1 12 t b16 urc_sq_vccaux33 12 urc_sq_vccaux33 12 e17 urc_sq_refclkn 12 c urc_sq_refclkn 12 c d17 urc_sq_refclkp 12 t urc_sq_refclkp 12 t c16 urc_sq_vccp 12 urc_sq_vccp 12 a12 urc_sq_hdinp2 12 t urc_sq_hdinp2 12 t c12 urc_sq_vccib2 12 urc_sq_vccib2 12 b12 urc_sq_hdinn2 12 c urc_sq_hdinn2 12 c c11 urc_sq_vccrx2 12 urc_sq_vccrx2 12 a15 urc_sq_hdoutp2 12 t urc_sq_hdoutp2 12 t c15 urc_sq_vccob2 12 urc_sq_vccob2 12 b15 urc_sq_hdoutn2 12 c urc_sq_hdoutn2 12 c c14 urc_sq_vcctx2 12 urc_sq_vcctx2 12 b14 urc_sq_hdoutn3 12 c urc_sq_hdoutn3 12 c a13 urc_sq_vccob3 12 urc_sq_vccob3 12 a14 urc_sq_hdoutp3 12 t urc_sq_hdoutp3 12 t c13 urc_sq_vcctx3 12 urc_sq_vcctx3 12 b11 urc_sq_hdinn3 12 c urc_sq_hdinn3 12 c b10 urc_sq_vccib3 12 urc_sq_vccib3 12 a11 urc_sq_hdinp3 12 t urc_sq_hdinp3 12 t c10 urc_sq_vccrx3 12 urc_sq_vccrx3 12 e13 pt28b 1 c pt46b 1 c d12 pt28a 1 t pt46a 1 t gndio gndio1 1 gndio1 1 a9 pt27b 1 c pt45b 1 c a8 pt27a 1 t pt45a 1 t a7 pt26b 1 c pt44b 1 c a6 pt26a 1 t pt44a 1 t lfem20e/20se and lfe2m35e/35se logic signal connections: 484 fpbga (cont.) lfe2m20e/20se lfe2m35e,/35se ball number ball function bank dual function differential ball function bank dual function differential
4-144 pinout information lattice semiconductor latticeecp2/m family data sheet vccio vccio1 1 vccio1 1 e12 pt25b 1 c pt43b 1 c f12 pt25a 1 t pt43a 1 t a5 pt24b 1 c pt42b 1 c a4 pt24a 1 t pt42a 1 t gndio gndio1 1 gndio1 1 b7 pt23b 1 c pt41b 1 c b8 pt23a 1 t pt41a 1 t g11 pt22b 1 c pt40b 1 c e11 pt22a 1 t pt40a 1 t vccio vccio1 1 vccio1 1 d11 pt21b 1 vref2_1 c pt39b 1 vref2_1 c d10 pt21a 1 vref1_1 t pt39a 1 vref1_1 t f11 pt20a 1 pclkt1_0 t pt38b 1 pclkc1_0 c g10 pt20b 1 pclkc1_0 c pt38a 1 pclkt1_0 t g9 pt19b 0 pclkc0_0 c pt37b 0 pclkc0_0 c gndio gndio0 0 gndio0 0 f9 pt19a 0 pclkt0_0 t pt37a 0 pclkt0_0 t c9 pt18b 0 vref2_0 c pt36b 0 vref2_0 c d9 pt18a 0 vref1_0 t pt36a 0 vref1_0 t a2 pt17b 0 c pt35b 0 c vccio vccio0 0 vccio0 0 a3 pt17a 0 t pt35a 0 t b3 pt16b 0 c pt34b 0 c c4 pt16a 0 t pt34a 0 t e10 pt15b 0 c pt33b 0 c f10 pt15a 0 t pt33a 0 t c7 pt14b 0 c pt32b 0 c gndio gndio0 0 gndio0 0 b6 pt14a 0 t pt32a 0 t c6 pt13b 0 c pt31b 0 c vccio vccio0 0 vccio0 0 c5 pt13a 0 t pt31a 0 t c8 pt12b 0 c pt30b 0 c d8 pt12a 0 t pt30a 0 t e8 pt11b 0 c pt29b 0 c e9 pt11a 0 t pt29a 0 t - - - gndio0 0 - - - vccio0 0 f8 pt10b 0 c pt10b 0 c g8 pt10a 0 t pt10a 0 t gndio gndio0 0 gndio0 0 f7 pt9b 0 c pt9b 0 c g7 pt9a 0 t pt9a 0 t c3 pt8b 0 c pt8b 0 c d4 pt8a 0 t pt8a 0 t vccio vccio0 0 vccio0 0 f6 pt7b 0 c pt7b 0 c lfem20e/20se and lfe2m35e/35se logic signal connections: 484 fpbga (cont.) lfe2m20e/20se lfe2m35e,/35se ball number ball function bank dual function differential ball function bank dual function differential
4-145 pinout information lattice semiconductor latticeecp2/m family data sheet e6 pt7a 0 t pt7a 0 t e5 pt6b 0 c pt6b 0 c d6 pt6a 0 t pt6a 0 t gndio gndio0 0 gndio0 0 d3 pt5b 0 c pt5b 0 c e3 pt5a 0 t pt5a 0 t d5 pt4b 0 c pt4b 0 c e4 pt4a 0 t pt4a 0 t vccio vccio0 0 vccio0 0 c2 pt3b 0 c pt3b 0 c b2 pt3a 0 t pt3a 0 t b1 pt2b 0 c pt2b 0 c c1 pt2a 0 t pt2a 0 t r8 vccpll - vccpll - h15 vccpll - vccpll - h8 vccpll - vccpll - r15 vccpll - vccpll - j10 vcc - vcc - j11 vcc - vcc - j12 vcc - vcc - j13 vcc - vcc - k14 vcc - vcc - k9 vcc - vcc - l14 vcc - vcc - l9 vcc - vcc - m14 vcc - vcc - m9 vcc - vcc - n14 vcc - vcc - n9 vcc - vcc - p10 vcc - vcc - p11 vcc - vcc - p12 vcc - vcc - p13 vcc - vcc - b5 vccio0 0 vccio0 0 b9 vccio0 0 vccio0 0 e7 vccio0 0 vccio0 0 h9 vccio0 0 vccio0 0 d13 vccio1 1 vccio1 1 e16 vccio1 1 vccio1 1 h14 vccio1 1 vccio1 1 e21 vccio2 2 vccio2 2 g18 vccio2 2 vccio2 2 j15 vccio2 2 vccio2 2 k19 vccio2 2 vccio2 2 n19 vccio3 3 vccio3 3 p15 vccio3 3 vccio3 3 t18 vccio3 3 vccio3 3 v21 vccio3 3 vccio3 3 lfem20e/20se and lfe2m35e/35se logic signal connections: 484 fpbga (cont.) lfe2m20e/20se lfe2m35e,/35se ball number ball function bank dual function differential ball function bank dual function differential
4-146 pinout information lattice semiconductor latticeecp2/m family data sheet aa18 vccio4 4 vccio4 4 r14 vccio4 4 vccio4 4 v16 vccio4 4 vccio4 4 w 13 vccio4 4 vccio4 4 aa5 vccio5 5 vccio5 5 r9 vccio5 5 vccio5 5 v7 vccio5 5 vccio5 5 w 10 vccio5 5 vccio5 5 n4 vccio6 6 vccio6 6 p8 vccio6 6 vccio6 6 t5 vccio6 6 vccio6 6 v2 vccio6 6 vccio6 6 e2 vccio7 7 vccio7 7 g5 vccio7 7 vccio7 7 j8 vccio7 7 vccio7 7 k4 vccio7 7 vccio7 7 aa22 vccio8 8 vccio8 8 u19 vccio8 8 vccio8 8 h11 vccaux - vccaux - h12 vccaux - vccaux - l15 vccaux - vccaux - l8 vccaux - vccaux - m15 vccaux - vccaux - m8 vccaux - vccaux - r11 vccaux - vccaux - r12 vccaux - vccaux - a1 gnd - gnd - a10 gnd - gnd - a16 gnd - gnd - a22 gnd - gnd - aa19 gnd - gnd - aa4 gnd - gnd - ab1 gnd - gnd - ab22 gnd - gnd - b13 gnd - gnd - b19 gnd - gnd - b4 gnd - gnd - d16 gnd - gnd - d2 gnd - gnd - d21 gnd - gnd - d7 gnd - gnd - g19 gnd - gnd - g4 gnd - gnd - h10 gnd - gnd - h13 gnd - gnd - j14 gnd - gnd - j9 gnd - gnd - k10 gnd - gnd - lfem20e/20se and lfe2m35e/35se logic signal connections: 484 fpbga (cont.) lfe2m20e/20se lfe2m35e,/35se ball number ball function bank dual function differential ball function bank dual function differential
4-147 pinout information lattice semiconductor latticeecp2/m family data sheet k11 gnd - gnd - k12 gnd - gnd - k13 gnd - gnd - k15 gnd - gnd - k20 gnd - gnd - k3 gnd - gnd - k8 gnd - gnd - l10 gnd - gnd - l11 gnd - gnd - l12 gnd - gnd - l13 gnd - gnd - m10 gnd - gnd - m11 gnd - gnd - m12 gnd - gnd - m13 gnd - gnd - n10 gnd - gnd - n11 gnd - gnd - n12 gnd - gnd - n13 gnd - gnd - n15 gnd - gnd - n20 gnd - gnd - n3 gnd - gnd - n8 gnd - gnd - p14 gnd - gnd - p9 gnd - gnd - r10 gnd - gnd - r13 gnd - gnd - t19 gnd - gnd - t4 gnd - gnd - w 16 gnd - gnd - w 2 gnd - gnd - w 21 gnd - gnd - w 7 gnd - gnd - y10 gnd - gnd - y13 gnd - gnd - d15 nc - nc - g14 nc - nc - g15 nc - nc - d14 nc - nc - e15 nc - nc - e14 nc - nc - f15 nc - nc - f14 nc - nc - f13 nc - nc - g12 nc - nc - g13 nc - nc - * supports true lvds. other differential signals must be emulated with external resistors. ** these dedicated input pins can be used for gplls or gdlls within the respective quadrant. lfem20e/20se and lfe2m35e/35se logic signal connections: 484 fpbga (cont.) lfe2m20e/20se lfe2m35e,/35se ball number ball function bank dual function differential ball function bank dual function differential
4-148 pinout information lattice semiconductor latticeecp2/m family data sheet lfe2m35e/35se logic signal connections: 672 fpbga lfe2m35e/35se ball number ball function bank dual function differential c2 pl2a 7 t (lvds)* c1 pl2b 7 c (lvds)* f6 pl3a 7 t h9 pl3b 7 c d3 pl4a 7 t (lvds)* vccio vccio7 7 d2 pl4b 7 c (lvds)* f5 pl5a 7 t h8 pl5b 7 c e3 pl6a 7 ldqs6 t (lvds)* gndio gndio7 7 e2 pl6b 7 c (lvds)* j9 pl7a 7 t e4 pl7b 7 c vccio vccio7 7 e1 pl8a 7 t (lvds)* d1 pl8b 7 c (lvds)* j8 pl9a 7 vref2_7 t f4 pl9b 7 vref1_7 c gndio gndio7 7 f3 pl11a 7 lum0_spllt_in_a t (lvds)* f1 pl11b 7 lum0_spllc_in_a c (lvds)* g6 pl12a 7 lum0_spllt_fb_a t k9 pl12b 7 lum0_spllc_fb_a c g5 pl13a 7 t (lvds)* vccio vccio7 7 g4 pl13b 7 c (lvds)* h5 pl14a 7 t h6 pl14b 7 c gndio gndio7 7 j7 pl16a 7 t h4 pl16b 7 c vccio vccio7 7 h3 pl17a 7 t (lvds)* g3 pl17b 7 c (lvds)* gndio gndio7 7 g1 pl19a 7 t (lvds)* h1 pl19b 7 c (lvds)* j3 pl20a 7 t j4 pl20b 7 c vccio vccio7 7 h2 pl21a 7 t (lvds)*
4-149 pinout information lattice semiconductor latticeecp2/m family data sheet j2 pl21b 7 c (lvds)* k7 pl22a 7 t j6 pl22b 7 c gndio gndio7 7 k5 pl23a 7 ldqs23 t (lvds)* l5 pl23b 7 c (lvds)* k4 pl24a 7 t vccio vccio7 7 l4 pl24b 7 c k3 pl25a 7 t (lvds)* l3 pl25b 7 c (lvds)* j1 pl26a 7 t gndio gndio7 7 k2 pl26b 7 c k1 pl28a 7 lum1_spllt_in_a t (lvds)* l1 pl28b 7 lum1_spllc_in_a c (lvds)* k8 pl29a 7 lum1_spllt_fb_a t m5 pl29b 7 lum1_spllc_fb_a c vccio vccio7 7 m4 pl30a 7 t (lvds)* m3 pl30b 7 c (lvds)* l8 pl31a 7 t m6 pl31b 7 c gndio gndio7 7 m1 pl32a 7 ldqs32 t (lvds)* n1 pl32b 7 c (lvds)* n3 pl33a 7 t vccio vccio7 7 n2 pl33b 7 c n5 pl34a 7 t (lvds)* n4 pl34b 7 c (lvds)* m7 pl35a 7 pclkt7_0 t gndio gndio7 7 m8 pl35b 7 pclkc7_0 c p3 pl37a 6 pclkt6_0 t (lvds)* p2 pl37b 6 pclkc6_0 c (lvds)* p5 pl38a 6 vref2_6 t n6 pl38b 6 vref1_6 c p4 pl39a 6 t (lvds)* vccio vccio6 6 r3 pl39b 6 c (lvds)* p6 pl40a 6 t p1 pl41a 6 llm2_spllt_in_a t (lvds)* lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-150 pinout information lattice semiconductor latticeecp2/m family data sheet gndio gndio6 6 r1 pl41b 6 llm2_spllc_in_a c (lvds)* n8 pl42a 6 llm2_spllt_fb_a t r5 pl42b 6 llm2_spllc_fb_a c vccio vccio6 6 t3 pl44a 6 t (lvds)* t4 pl44b 6 c (lvds)* p8 pl45a 6 t r6 pl45b 6 c vccio vccio6 6 t1 pl46a 6 t (lvds)* u1 pl46b 6 c (lvds)* r7 pl47a 6 t t5 pl47b 6 c gndio gndio6 6 u3 pl48a 6 ldqs48 t (lvds)* u4 pl48b 6 c (lvds)* u5 pl49a 6 t vccio vccio6 6 u6 pl49b 6 c u2 pl50a 6 t (lvds)* v1 pl50b 6 c (lvds)* w 2 pl51a 6 t gndio gndio6 6 v2 pl51b 6 c v4 pl55a 6 t (lvds)* vccio vccio6 6 v3 pl55b 6 c (lvds)* w 4 pl57a 6 llm0_gpllt_in_a**/ldqs57 t (lvds)* gndio gndio6 6 w 3 pl57b 6 llm0_gpllc_in_a** c (lvds)* w 1 pl58a 6 llm0_gpllt_fb_a t y1 pl58b 6 llm0_gpllc_fb_a c vccio vccio6 6 aa1 pl59a 6 llm0_gdllt_in_a** t (lvds)* ab1 pl59b 6 llm0_gdllc_in_a** c (lvds)* u7 pl60a 6 llm0_gdllt_fb_a t v6 pl60b 6 llm0_gdllc_fb_a c gndio gndio6 6 t8 llm0_pllcap 6 w 5 pl62a 6 t (lvds)* y4 pl62b 6 c (lvds)* u8 pl63a 6 t lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-151 pinout information lattice semiconductor latticeecp2/m family data sheet w 6 pl63b 6 c vccio vccio6 6 y3 pl64a 6 t (lvds)* aa3 pl64b 6 c (lvds)* y5 pl65b 6 c gndio gndio6 6 ab2 pl66a 6 ldqs66 t (lvds)* aa4 pl66b 6 c (lvds)* y6 pl67a 6 t vccio vccio6 6 u9 pl67b 6 c aa5 pl68a 6 t (lvds)* aa6 pl68b 6 c (lvds)* y7 pl69a 6 t gndio gndio6 6 v9 pl69b 6 c ac3 tck - w 8 tdi - ac4 tms - v8 tdo - aa7 vccj - ab6 pb2a 5 t y8 pb2b 5 c ad1 pb3a 5 t ad2 pb3b 5 c ac5 pb4a 5 t vccio vccio5 5 aa8 pb4b 5 c ac6 pb5a 5 t w 9 pb5b 5 c ab7 pb6a 5 bdqs6 t gndio gndio5 5 y9 pb6b 5 c ad3 pb7a 5 t ad4 pb7b 5 c aa9 pb8a 5 t vccio vccio5 5 w 10 pb8b 5 c ac7 pb9a 5 t y10 pb9b 5 c ae2 pb10a 5 t gndio gndio5 5 ad5 pb10b 5 c lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-152 pinout information lattice semiconductor latticeecp2/m family data sheet ae4 pb11a 5 t ae3 pb11b 5 c w 11 pb12a 5 t ab8 pb12b 5 c ae5 pb13a 5 t ad6 pb13b 5 c vccio vccio5 5 aa10 pb14a 5 t ac8 pb14b 5 c gndio gndio5 5 w 12 pb15a 5 bdqs15 t ac9 pb15b 5 c w 13 pb16a 5 t ab10 pb16b 5 c af3 pb17a 5 t af4 pb17b 5 c vccio vccio5 5 af5 pb18a 5 t af6 pb18b 5 c y12 pb19a 5 t ab11 pb19b 5 c gndio gndio5 5 ad7 pb20a 5 t af7 pb20b 5 c ad8 pb21a 5 t aa12 pb21b 5 c ae8 pb22a 5 t vccio vccio5 5 af8 pb22b 5 c ad9 pb23a 5 t ac10 pb23b 5 c ac11 pb24a 5 bdqs24 t gndio gndio5 5 ab12 pb24b 5 c ad10 pb25a 5 t y13 pb25b 5 c af9 pb26a 5 t vccio vccio5 5 ae9 pb26b 5 c af10 pb27a 5 t ae10 pb27b 5 c ad11 pb28a 5 t gndio gndio5 5 lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-153 pinout information lattice semiconductor latticeecp2/m family data sheet af11 pb28b 5 c vccio vccio5 5 gndio gndio5 5 aa13 pb33a 5 bdqs33 t ab13 pb33b 5 c w 14 pb34a 5 vref2_5 t ac12 pb34b 5 vref1_5 c af12 pb35a 5 pclkt5_0 t ad12 pb35b 5 pclkc5_0 c vccio vccio5 5 gndio gndio5 5 ac13 pb40a 4 pclkt4_0 t vccio vccio4 4 y14 pb40b 4 pclkc4_0 c ae14 pb41a 4 vref2_4 t ac14 pb41b 4 vref1_4 c ab14 pb42a 4 bdqs42 t gndio gndio4 4 aa14 pb42b 4 c vccio vccio4 4 gndio gndio4 4 af14 pb47a 4 t af15 pb47b 4 c ac15 pb48a 4 t ae15 pb48b 4 c ab15 pb49a 4 t ac16 pb49b 4 c vccio vccio4 4 ae17 pb50a 4 t ab16 pb50b 4 c gndio gndio4 4 aa15 pb51a 4 bdqs51 t af17 pb51b 4 c y15 pb52a 4 t ac17 pb52b 4 c af18 pb53a 4 t ae18 pb53b 4 c vccio vccio4 4 w 15 pb54a 4 t ab17 pb54b 4 c af20 pb55a 4 t ae20 pb55b 4 c gndio gndio4 4 lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-154 pinout information lattice semiconductor latticeecp2/m family data sheet ab20 pb57a 4 t ac19 pb57b 4 c ac20 pb58a 4 t vccio vccio4 4 ab19 pb59a 4 t w 16 pb59b 4 c aa17 pb60a 4 bdqs60 t gndio gndio4 4 aa18 pb61a 4 t y17 pb61b 4 c af21 pb62a 4 t vccio vccio4 4 ac21 pb63a 4 t ae21 pb63b 4 c af23 pb64a 4 t gndio gndio4 4 w 17 pb65a 4 t aa19 pb65b 4 c ae23 pb66b 4 c af24 pb67a 4 t ae24 pb67b 4 c vccio vccio4 4 y18 pb68b 4 c gndio gndio4 4 ac22 pb69a 4 bdqs69 t ab21 pb69b 4 c ad26 pb70b 4 c ac23 pb71a 4 t ac25 pb71b 4 c vccio vccio4 4 w 20 pb72b 4 c v17 pb73a 4 t aa20 pb73b 4 c gndio gndio4 4 aa21 cfg2 8 aa22 cfg1 8 ab23 cfg0 8 ac26 programn 8 ab24 cclk 8 aa23 initn 8 ab25 done 8 gndio gndio8 8 y19 pr68b 8 w riten c lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-155 pinout information lattice semiconductor latticeecp2/m family data sheet y21 pr68a 8 cs1n t ab26 pr67b 8 csn c y22 pr67a 8 d0 t vccio vccio8 8 w 19 pr66b 8 d1 c y20 pr66a 8 d2 t w 22 pr65b 8 d3 c gndio gndio8 8 w 18 pr65a 8 d4 t y23 pr64b 8 d5 c aa24 pr64a 8 d6 t w 21 pr63b 8 d7 c vccio vccio8 8 v20 pr63a 8 di t w 23 pr62b 8 dout_cson c y24 pr62a 8 busy t v19 rlm0_pllcap 3 v21 pr60b 3 rlm0_gdllc_fb_a c gndio gndio3 3 u19 pr60a 3 rlm0_gdllt_fb_a t aa26 pr59b 3 rlm0_gdllc_in_a** c (lvds)* y26 pr59a 3 rlm0_gdllt_in_a** t (lvds)* v23 pr58b 3 rlm0_gpllc_in_a** c vccio vccio3 3 u20 pr58a 3 rlm0_gpllt_in_a** t w 24 pr57b 3 rlm0_gpllc_fb_a c (lvds)* v24 pr57a 3 rlm0_gpllt_fb_a/rdqs57 t (lvds)* gndio gndio3 3 u21 pr56a 3 t w 25 pr55b 3 c (lvds)* w 26 pr55a 3 t (lvds)* vccio vccio3 3 u18 pr54b 3 c u22 pr54a 3 t v25 pr53b 3 c (lvds)* v26 pr53a 3 t (lvds)* u24 pr51b 3 c t24 pr51a 3 t gndio gndio3 3 t22 pr50b 3 c (lvds)* t23 pr50a 3 t (lvds)* u25 pr49b 3 c u26 pr49a 3 t lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-156 pinout information lattice semiconductor latticeecp2/m family data sheet vccio vccio3 3 t19 pr48b 3 c (lvds)* r19 pr48a 3 rdqs48 t (lvds)* r21 pr47b 3 c gndio gndio3 3 r20 pr47a 3 t t26 pr46b 3 c (lvds)* r26 pr46a 3 t (lvds)* p21 pr45b 3 c vccio vccio3 3 p19 pr45a 3 t r23 pr44b 3 c (lvds)* r24 pr44a 3 t (lvds)* r22 pr42b 3 rlm2_spllc_fb_a c vccio vccio3 3 n19 pr42a 3 rlm2_spllt_fb_a t p23 pr41b 3 rlm2_spllc_in_a c (lvds)* p24 pr41a 3 rlm2_spllt_in_a t (lvds)* gndio gndio3 3 n21 pr40b 3 c p22 pr40a 3 t n20 pr39b 3 c (lvds)* n22 pr39a 3 t (lvds)* vccio vccio3 3 p25 pr38b 3 vref2_3 c p26 pr38a 3 vref1_3 t m21 pr37b 3 pclkc3_0 c (lvds)* n23 pr37a 3 pclkt3_0 t (lvds)* n24 pr35b 2 pclkc2_0 c n25 pr35a 2 pclkt2_0 t gndio gndio2 2 m22 pr34b 2 c (lvds)* m24 pr34a 2 t (lvds)* m23 pr33b 2 c n26 pr33a 2 t vccio vccio2 2 l22 pr32b 2 c (lvds)* l24 pr32a 2 rdqs32 t (lvds)* l23 pr31b 2 c gndio gndio2 2 m20 pr31a 2 t m26 pr30b 2 c (lvds)* l26 pr30a 2 t (lvds)* lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-157 pinout information lattice semiconductor latticeecp2/m family data sheet k22 pr29b 2 rum1_spllc_fb_a c vccio vccio2 2 m19 pr29a 2 rum1_spllt_fb_a t k25 pr28b 2 rum1_spllc_in_a c (lvds)* k26 pr28a 2 rum1_spllt_in_a t (lvds)* k24 pr26b 2 c k23 pr26a 2 t gndio gndio2 2 l19 pr25b 2 c (lvds)* k21 pr25a 2 t (lvds)* j23 pr24b 2 c j24 pr24a 2 t vccio vccio2 2 k20 pr23b 2 c (lvds)* j21 pr23a 2 rdqs23 t (lvds)* h21 pr22b 2 c gndio gndio2 2 k18 pr22a 2 t h22 pr21b 2 c (lvds)* j20 pr21a 2 t (lvds)* j25 pr20b 2 c vccio vccio2 2 j26 pr20a 2 t g21 pr19b 2 c (lvds)* j19 pr19a 2 t (lvds)* h23 pr18b 2 c gndio gndio2 2 h24 pr18a 2 t h25 pr17b 2 c (lvds)* h26 pr17a 2 t (lvds)* g22 pr16b 2 c vccio vccio2 2 k19 pr16a 2 t g24 pr15b 2 c (lvds)* g23 pr15a 2 rdqs15 t (lvds)* gndio gndio2 2 j18 pr14b 2 c f22 pr14a 2 t f23 pr13b 2 c (lvds)* f24 pr13a 2 t (lvds)* vccio vccio2 2 h20 pr12b 2 rum0_spllc_fb_a c f21 pr12a 2 rum0_spllt_fb_a t lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-158 pinout information lattice semiconductor latticeecp2/m family data sheet g26 pr11b 2 rum0_spllc_in_a c (lvds)* f26 pr11a 2 rum0_spllt_in_a t (lvds)* e24 pr9b 2 vref2_2 c gndio gndio2 2 e23 pr9a 2 vref1_2 t h19 xres - c25 urc_sq_vccrx0 12 a24 urc_sq_hdinp0 12 t b25 urc_sq_vccib0 12 b24 urc_sq_hdinn0 12 c c22 urc_sq_vcctx0 12 a21 urc_sq_hdoutp0 12 t a22 urc_sq_vccob0 12 b21 urc_sq_hdoutn0 12 c c21 urc_sq_vcctx1 12 b20 urc_sq_hdoutn1 12 c c20 urc_sq_vccob1 12 a20 urc_sq_hdoutp1 12 t c24 urc_sq_vccrx1 12 b23 urc_sq_hdinn1 12 c c23 urc_sq_vccib1 12 a23 urc_sq_hdinp1 12 t b19 urc_sq_vccaux33 12 e19 urc_sq_refclkn 12 c d19 urc_sq_refclkp 12 t c19 urc_sq_vccp 12 a15 urc_sq_hdinp2 12 t c15 urc_sq_vccib2 12 b15 urc_sq_hdinn2 12 c c14 urc_sq_vccrx2 12 a18 urc_sq_hdoutp2 12 t c18 urc_sq_vccob2 12 b18 urc_sq_hdoutn2 12 c c17 urc_sq_vcctx2 12 b17 urc_sq_hdoutn3 12 c a16 urc_sq_vccob3 12 a17 urc_sq_hdoutp3 12 t c16 urc_sq_vcctx3 12 b14 urc_sq_hdinn3 12 c b13 urc_sq_vccib3 12 a14 urc_sq_hdinp3 12 t c13 urc_sq_vccrx3 12 e17 pt46b 1 c lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-159 pinout information lattice semiconductor latticeecp2/m family data sheet d17 pt46a 1 t gndio gndio1 1 f17 pt45b 1 c d16 pt45a 1 t f19 pt44b 1 c f18 pt44a 1 t vccio vccio1 1 e16 pt43b 1 c d15 pt43a 1 t g18 pt42b 1 c e15 pt42a 1 t gndio gndio1 1 g17 pt41b 1 c e14 pt41a 1 t d14 pt40b 1 c d13 pt40a 1 t vccio vccio1 1 f15 pt39b 1 vref2_1 c e12 pt39a 1 vref1_1 t h17 pt38b 1 pclkc1_0 c e13 pt38a 1 pclkt1_0 t c12 pt37b 0 pclkc0_0 c gndio gndio0 0 g15 pt37a 0 pclkt0_0 t c11 pt36b 0 vref2_0 c f14 pt36a 0 vref1_0 t a12 pt35b 0 c vccio vccio0 0 a11 pt35a 0 t d12 pt34b 0 c h16 pt34a 0 t h18 pt33b 0 c h15 pt33a 0 t a10 pt32b 0 c gndio gndio0 0 b10 pt32a 0 t d11 pt31b 0 c vccio vccio0 0 g14 pt31a 0 t e11 pt30b 0 c f13 pt30a 0 t d10 pt29b 0 c h14 pt29a 0 t lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-160 pinout information lattice semiconductor latticeecp2/m family data sheet gndio gndio0 0 vccio vccio0 0 a9 pt24b 0 c gndio gndio0 0 c10 pt23b 0 c e8 pt23a 0 t b9 pt22b 0 c a8 pt22a 0 t vccio vccio0 0 f12 pt21b 0 c e10 pt21a 0 t g13 pt20b 0 c c9 pt20a 0 t b8 pt19b 0 c gndio gndio0 0 a7 pt19a 0 t d9 pt18b 0 c h13 pt18a 0 t d6 pt17b 0 c vccio vccio0 0 c7 pt17a 0 t c8 pt16b 0 c g12 pt16a 0 t d8 pt15b 0 c h12 pt15a 0 t a6 pt14b 0 c gndio gndio0 0 a5 pt14a 0 t a4 pt13b 0 c vccio vccio0 0 a3 pt13a 0 t c6 pt12b 0 c f10 pt12a 0 t d7 pt11b 0 c h11 pt11a 0 t d5 pt10b 0 c e6 pt10a 0 t gndio gndio0 0 g10 pt9b 0 c f9 pt9a 0 t h10 pt8b 0 c e7 pt8a 0 t vccio vccio0 0 lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-161 pinout information lattice semiconductor latticeecp2/m family data sheet b3 pt7b 0 c c5 pt7a 0 t b2 pt6b 0 c c4 pt6a 0 t gndio gndio0 0 g9 pt5b 0 c f7 pt5a 0 t c3 pt4b 0 c d4 pt4a 0 t vccio vccio0 0 j10 pt3b 0 c f8 pt3a 0 t g8 pt2b 0 c g7 pt2a 0 t h7 l_vccpll - k6 l_vccpll - p7 l_vccpll - r8 l_vccpll - v18 r_vccpll - p20 r_vccpll - j17 r_vccpll - g19 r_vccpll - ad13 vcc - ad14 vcc - ad16 vcc - ad17 vcc - ad19 vcc - ad21 vcc - ad22 vcc - ad24 vcc - ad25 vcc - l12 vcc - l13 vcc - l14 vcc - l15 vcc - m11 vcc - m12 vcc - m15 vcc - m16 vcc - n11 vcc - n16 vcc - p11 vcc - p16 vcc - lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-162 pinout information lattice semiconductor latticeecp2/m family data sheet r11 vcc - r12 vcc - r15 vcc - r16 vcc - t12 vcc - t13 vcc - t14 vcc - t15 vcc - b12 vccio0 0 b7 vccio0 0 f11 vccio0 0 j13 vccio0 0 k12 vccio0 0 d18 vccio1 1 f16 vccio1 1 j14 vccio1 1 k15 vccio1 1 g25 vccio2 2 l21 vccio2 2 m17 vccio2 2 m25 vccio2 2 n18 vccio2 2 p18 vccio3 3 r17 vccio3 3 r25 vccio3 3 t21 vccio3 3 y25 vccio3 3 aa16 vccio4 4 ac18 vccio4 4 u15 vccio4 4 v14 vccio4 4 aa11 vccio5 5 ae12 vccio5 5 ae7 vccio5 5 u12 vccio5 5 v13 vccio5 5 p9 vccio6 6 r10 vccio6 6 r2 vccio6 6 t6 vccio6 6 y2 vccio6 6 g2 vccio7 7 l6 vccio7 7 lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-163 pinout information lattice semiconductor latticeecp2/m family data sheet m10 vccio7 7 m2 vccio7 7 n9 vccio7 7 ac24 vccio8 8 u17 vccio8 8 ae19 vccaux - j11 vccaux - j12 vccaux - j15 vccaux - j16 vccaux - l18 vccaux - l9 vccaux - m18 vccaux - m9 vccaux - r18 vccaux - r9 vccaux - t18 vccaux - t9 vccaux - v11 vccaux - v12 vccaux - v15 vccaux - v16 vccaux - a13 gnd - a19 gnd - a2 gnd - a25 gnd - aa2 gnd - aa25 gnd - ab18 gnd - ab22 gnd - ab5 gnd - ab9 gnd - ae1 gnd - ae11 gnd - ae16 gnd - ae22 gnd - ae26 gnd - ae6 gnd - af13 gnd - af19 gnd - af2 gnd - af25 gnd - b1 gnd - lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-164 pinout information lattice semiconductor latticeecp2/m family data sheet b11 gnd - b16 gnd - b22 gnd - b26 gnd - b6 gnd - e18 gnd - e22 gnd - e5 gnd - e9 gnd - f2 gnd - f25 gnd - g11 gnd - g16 gnd - j22 gnd - j5 gnd - k11 gnd - k13 gnd - k14 gnd - k16 gnd - l10 gnd - l11 gnd - l16 gnd - l17 gnd - l2 gnd - l20 gnd - l25 gnd - l7 gnd - m13 gnd - m14 gnd - n10 gnd - n12 gnd - n13 gnd - n14 gnd - n15 gnd - n17 gnd - p10 gnd - p12 gnd - p13 gnd - p14 gnd - p15 gnd - p17 gnd - r13 gnd - r14 gnd - lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-165 pinout information lattice semiconductor latticeecp2/m family data sheet t10 gnd - t11 gnd - t16 gnd - t17 gnd - t2 gnd - t20 gnd - t25 gnd - t7 gnd - u11 gnd - u13 gnd - u14 gnd - u16 gnd - v22 gnd - v5 gnd - y11 gnd - y16 gnd - ab3 nc - ab4 nc - ac1 nc - ac2 nc - ad15 nc - ad18 nc - ad20 nc - ad23 nc - ae13 nc - ae25 nc - af16 nc - af22 nc - b4 nc - b5 nc - c26 nc - d20 nc - d21 nc - d22 nc - d23 nc - d24 nc - d25 nc - d26 nc - e20 nc - e21 nc - e25 nc - e26 nc - f20 nc - lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
4-166 pinout information lattice semiconductor latticeecp2/m family data sheet g20 nc - k10 nc - k17 nc - r4 nc - u10 nc - u23 nc - v10 nc - w 7nc- n7 nc - v7 nc - * supports true lvds. other differential signals must be emulated with external resistors. ** these dedicated input pins can be used for gplls or gdlls within the respective quadrant. lfe2m35e/35se logic signal connections: 672 fpbga (cont.) lfe2m35e/35se ball number ball function bank dual function differential
www.latticesemi.com 5-1 ds1006 order info_01.4 april 2007 advance data sheet ds1006 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. latticeecp2 part number description ordering information note: latticeecp2 devices are dual marked. for example, the commercial speed grade lfe2-50e-7f672c is also marked with industrial grade -6i (lfe2-50e-6f672i). the commercial grade is one speed grade faster than the associated dual mark industrial grade. the slowest commercial speed grade does not have industrial markings. the markings appear as follows: lfe2 ?xx xe ?x xxxxxx x grade c = commercial i = industrial logic capacity 6 = 6k luts 12 = 12k luts 20 = 20k luts 35 = 35k luts 50 = 50k luts 70 = 70k luts supply voltage e = 1.2v encryption s = security series (encryption feature) blank = standard series (no encryption) speed 5 = slowest 6 7 = fastest package t144 = 144-pin tqfp q208 = 208-pin pqfp f256 = 256-ball fpbga f484 = 484-ball fpbga f672 = 672-ball fpbga f900 = 900-ball fpbga tn144 = 144-pin lead-free tqfp qn208 = 208-pin lead-free pqfp fn256 = 256-ball lead-free fpbga fn484 = 484-ball lead-free fpbga fn672 = 672-ball lead-free fpbga fn900 = 900-ball lead-free fpbga device family ecp2 (latticeecp2 fpga) lfe2-50e 7f672c-6i datecode lfe2-50se 7f672c-6i datecode contact your local lattice sales representative for product availability. latticeecp2/m family data sheet ordering information
5-2 ordering information lattice semiconductor latticeecp2/m family data sheet latticeecp2 standard series devices, conventional packaging commercial part number i/os voltage grade package pins temp. luts (k) lfe2-6e-5t144c 90 1.2v -5 tqfp 144 com 6 lfe2-6e-6t144c 90 1.2v -6 tqfp 144 com 6 lfe2-6e-7t144c 90 1.2v -7 tqfp 144 com 6 lfe2-6e-5f256c 190 1.2v -5 fpbga 256 com 6 lfe2-6e-6f256c 190 1.2v -6 fpbga 256 com 6 lfe2-6e-7f256c 190 1.2v -7 fpbga 256 com 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12e-5t144c 93 1.2v -5 tqfp 144 com 12 lfe2-12e-6t144c 93 1.2v -6 tqfp 144 com 12 lfe2-12e-7t144c 93 1.2v -7 tqfp 144 com 12 lfe2-12e-5q208c 131 1.2v -5 pqfp 208 com 12 lfe2-12e-6q208c 131 1.2v -6 pqfp 208 com 12 lfe2-12e-7q208c 131 1.2v -7 pqfp 208 com 12 lfe2-12e-5f256c 193 1.2v -5 fpbga 256 com 12 lfe2-12e-6f256c 193 1.2v -6 fpbga 256 com 12 lfe2-12e-7f256c 193 1.2v -7 fpbga 256 com 12 lfe2-12e-5f484c 297 1.2v -5 fpbga 484 com 12 lfe2-12e-6f484c 297 1.2v -6 fpbga 484 com 12 lfe2-12e-7f484c 297 1.2v -7 fpbga 484 com 12 part number i/os voltage grade package pins temp. luts (k) lfe2-20e-5q208c 131 1.2v -5 pqfp 208 com 20 lfe2-20e-6q208c 131 1.2v -6 pqfp 208 com 20 lfe2-20e-7q208c 131 1.2v -7 pqfp 208 com 20 lfe2-20e-5f256c 193 1.2v -5 fpbga 256 com 20 lfe2-20e-6f256c 193 1.2v -6 fpbga 256 com 20 lfe2-20e-7f256c 193 1.2v -7 fpbga 256 com 20 lfe2-20e-5f484c 331 1.2v -5 fpbga 484 com 20 lfe2-20e-6f484c 331 1.2v -6 fpbga 484 com 20 lfe2-20e-7f484c 331 1.2v -7 fpbga 484 com 20 lfe2-20e-5f672c 402 1.2v -5 fpbga 672 com 20 lfe2-20e-6f672c 402 1.2v -6 fpbga 672 com 20 lfe2-20e-7f672c 402 1.2v -7 fpbga 672 com 20
5-3 ordering information lattice semiconductor latticeecp2/m family data sheet industrial part number i/os voltage grade package pins temp. luts (k) lfe2-35e-5f484c 331 1.2v -5 fpbga 484 com 35 lfe2-35e-6f484c 331 1.2v -6 fpbga 484 com 35 lfe2-35e-7f484c 331 1.2v -7 fpbga 484 com 35 lfe2-35e-5f672c 450 1.2v -5 fpbga 672 com 35 lfe2-35e-6f672c 450 1.2v -6 fpbga 672 com 35 lfe2-35e-7f672c 450 1.2v -7 fpbga 672 com 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50e-5f484c 339 1.2v -5 fpbga 484 com 50 lfe2-50e-6f484c 339 1.2v -6 fpbga 484 com 50 lfe2-50e-7f484c 339 1.2v -7 fpbga 484 com 50 lfe2-50e-5f672c 500 1.2v -5 fpbga 672 com 50 lfe2-50e-6f672c 500 1.2v -6 fpbga 672 com 50 lfe2-50e-7f672c 500 1.2v -7 fpbga 672 com 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70e-5f672c 500 1.2v -5 fpbga 672 com 70 lfe2-70e-6f672c 500 1.2v -6 fpbga 672 com 70 lfe2-70e-7f672c 500 1.2v -7 fpbga 672 com 70 lfe2-70e-5f900c 588 1.2v -5 fpbga 900 com 70 lfe2-70e-6f900c 588 1.2v -6 fpbga 900 com 70 lfe2-70e-7f900c 588 1.2v -7 fpbga 900 com 70 part number i/os voltage grade package pins temp. luts (k) lfe2-6e-5t144i 90 1.2v -5 tqfp 144 ind 6 lfe2-6e-6t144i 90 1.2v -6 tqfp 144 ind 6 lfe2-6e-5f256i 190 1.2v -5 fpbga 256 ind 6 lfe2-6e-6f256i 190 1.2v -6 fpbga 256 ind 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12e-5t144i 93 1.2v -5 tqfp 144 ind 12 lfe2-12e-6t144i 93 1.2v -6 tqfp 144 ind 12 lfe2-12e-5q208i 131 1.2v -5 pqfp 208 ind 12 lfe2-12e-6q208i 131 1.2v -6 pqfp 208 ind 12 lfe2-12e-5f256i 193 1.2v -5 fpbga 256 ind 12 lfe2-12e-6f256i 193 1.2v -6 fpbga 256 ind 12 lfe2-12e-5f484i 297 1.2v -5 fpbga 484 ind 12 lfe2-12e-6f484i 297 1.2v -6 fpbga 484 ind 12
5-4 ordering information lattice semiconductor latticeecp2/m family data sheet part number i/os voltage grade package pins temp. luts (k) lfe2-20e-5q208i 131 1.2v -5 pqfp 208 ind 20 lfe2-20e-6q208i 131 1.2v -6 pqfp 208 ind 20 lfe2-20e-5f256i 193 1.2v -5 fpbga 256 ind 20 lfe2-20e-6f256i 193 1.2v -6 fpbga 256 ind 20 lfe2-20e-5f484i 331 1.2v -5 fpbga 484 ind 20 lfe2-20e-6f484i 331 1.2v -6 fpbga 484 ind 20 lfe2-20e-5f672i 402 1.2v -5 fpbga 672 ind 20 lfe2-20e-6f672i 402 1.2v -6 fpbga 672 ind 20 part number i/os voltage grade package pins temp. luts (k) lfe2-35e-5f484i 331 1.2v -5 fpbga 484 ind 35 lfe2-35e-6f484i 331 1.2v -6 fpbga 484 ind 35 lfe2-35e-5f672i 450 1.2v -5 fpbga 672 ind 35 lfe2-35e-6f672i 450 1.2v -6 fpbga 672 ind 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50e-5f484i 339 1.2v -5 fpbga 484 ind 50 lfe2-50e-6f484i 339 1.2v -6 fpbga 484 ind 50 lfe2-50e-5f672i 500 1.2v -5 fpbga 672 ind 50 lfe2-50e-6f672i 500 1.2v -6 fpbga 672 ind 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70e-5f672i 500 1.2v -5 fpbga 672 ind 70 lfe2-70e-6f672i 500 1.2v -6 fpbga 672 ind 70 lfe2-70e-5f900i 588 1.2v -5 fpbga 900 ind 70 lfe2-70e-6f900i 588 1.2v -6 fpbga 900 ind 70
5-5 ordering information lattice semiconductor latticeecp2/m family data sheet latticeecp2 standard series devices, lead-free packaging commercial part number i/os voltage grade package pins temp. luts (k) lfe2-6e-5tn144c 90 1.2v -5 lead-free tqfp 144 com 6 lfe2-6e-6tn144c 90 1.2v -6 lead-free tqfp 144 com 6 lfe2-6e-7tn144c 90 1.2v -7 lead-free tqfp 144 com 6 lfe2-6e-5fn256c 190 1.2v -5 lead-free fpbga 256 com 6 lfe2-6e-6fn256c 190 1.2v -6 lead-free fpbga 256 com 6 lfe2-6e-7fn256c 190 1.2v -7 lead-free fpbga 256 com 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12e-5tn144c 93 1.2v -5 lead-free tqfp 144 com 12 lfe2-12e-6tn144c 93 1.2v -6 lead-free tqfp 144 com 12 lfe2-12e-7tn144c 93 1.2v -7 lead-free tqfp 144 com 12 lfe2-12e-5qn208c 131 1.2v -5 lead-free pqfp 208 com 12 lfe2-12e-6qn208c 131 1.2v -6 lead-free pqfp 208 com 12 lfe2-12e-7qn208c 131 1.2v -7 lead-free pqfp 208 com 12 lfe2-12e-5fn256c 193 1.2v -5 lead-free fpbga 256 com 12 lfe2-12e-6fn256c 193 1.2v -6 lead-free fpbga 256 com 12 lfe2-12e-7fn256c 193 1.2v -7 lead-free fpbga 256 com 12 lfe2-12e-5fn484c 297 1.2v -5 lead-free fpbga 484 com 12 lfe2-12e-6fn484c 297 1.2v -6 lead-free fpbga 484 com 12 lfe2-12e-7fn484c 297 1.2v -7 lead-free fpbga 484 com 12 part number i/os voltage grade package pins temp. luts (k) lfe2-20e-5qn208c 131 1.2v -5 lead-free pqfp 208 com 20 lfe2-20e-6qn208c 131 1.2v -6 lead-free pqfp 208 com 20 lfe2-20e-7qn208c 131 1.2v -7 lead-free pqfp 208 com 20 lfe2-20e-5fn256c 193 1.2v -5 lead-free fpbga 256 com 20 lfe2-20e-6fn256c 193 1.2v -6 lead-free fpbga 256 com 20 lfe2-20e-7fn256c 193 1.2v -7 lead-free fpbga 256 com 20 lfe2-20e-5fn484c 331 1.2v -5 lead-free fpbga 484 com 20 lfe2-20e-6fn484c 331 1.2v -6 lead-free fpbga 484 com 20 lfe2-20e-7fn484c 331 1.2v -7 lead-free fpbga 484 com 20 lfe2-20e-5fn672c 402 1.2v -5 lead-free fpbga 672 com 20 lfe2-20e-6fn672c 402 1.2v -6 lead-free fpbga 672 com 20 lfe2-20e-7fn672c 402 1.2v -7 lead-free fpbga 672 com 20
5-6 ordering information lattice semiconductor latticeecp2/m family data sheet industrial part number i/os voltage grade package pins temp. luts (k) lfe2-35e-5fn484c 331 1.2v -5 lead-free fpbga 484 com 35 lfe2-35e-6fn484c 331 1.2v -6 lead-free fpbga 484 com 35 lfe2-35e-7fn484c 331 1.2v -7 lead-free fpbga 484 com 35 lfe2-35e-5fn672c 450 1.2v -5 lead-free fpbga 672 com 35 lfe2-35e-6fn672c 450 1.2v -6 lead-free fpbga 672 com 35 lfe2-35e-7fn672c 450 1.2v -7 lead-free fpbga 672 com 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50e-5fn484c 339 1.2v -5 lead-free fpbga 484 com 50 lfe2-50e-6fn484c 339 1.2v -6 lead-free fpbga 484 com 50 lfe2-50e-7fn484c 339 1.2v -7 lead-free fpbga 484 com 50 lfe2-50e-5fn672c 500 1.2v -5 lead-free fpbga 672 com 50 lfe2-50e-6fn672c 500 1.2v -6 lead-free fpbga 672 com 50 lfe2-50e-7fn672c 500 1.2v -7 lead-free fpbga 672 com 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70e-5fn672c 500 1.2v -5 lead-free fpbga 672 com 70 lfe2-70e-6fn672c 500 1.2v -6 lead-free fpbga 672 com 70 lfe2-70e-7fn672c 500 1.2v -7 lead-free fpbga 672 com 70 lfe2-70e-5fn900c 583 1.2v -5 lead-free fpbga 900 com 70 lfe2-70e-6fn900c 583 1.2v -6 lead-free fpbga 900 com 70 lfe2-70e-7fn900c 583 1.2v -7 lead-free fpbga 900 com 70 part number i/os voltage grade package pins temp. luts (k) lfe2-6e-5tn144i 90 1.2v -5 lead-free tqfp 144 ind 6 lfe2-6e-6tn144i 90 1.2v -6 lead-free tqfp 144 ind 6 lfe2-6e-5fn256i 190 1.2v -5 lead-free fpbga 256 ind 6 lfe2-6e-6fn256i 190 1.2v -6 lead-free fpbga 256 ind 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12e-5tn144i 93 1.2v -5 lead-free tqfp 144 ind 12 lfe2-12e-6tn144i 93 1.2v -6 lead-free tqfp 144 ind 12 lfe2-12e-5qn208i 131 1.2v -5 lead-free pqfp 208 ind 12 lfe2-12e-6qn208i 131 1.2v -6 lead-free pqfp 208 ind 12 lfe2-12e-5fn256i 193 1.2v -5 lead-free fpbga 256 ind 12 lfe2-12e-6fn256i 193 1.2v -6 lead-free fpbga 256 ind 12 lfe2-12e-5fn484i 297 1.2v -5 lead-free fpbga 484 ind 12 lfe2-12e-6fn484i 297 1.2v -6 lead-free fpbga 484 ind 12
5-7 ordering information lattice semiconductor latticeecp2/m family data sheet part number i/os voltage grade package pins temp. luts (k) lfe2-20e-5qn208i 131 1.2v -5 lead-free pqfp 208 ind 20 lfe2-20e-6qn208i 131 1.2v -6 lead-free pqfp 208 ind 20 lfe2-20e-5fn256i 193 1.2v -5 lead-free fpbga 256 ind 20 lfe2-20e-6fn256i 193 1.2v -6 lead-free fpbga 256 ind 20 lfe2-20e-5fn484i 331 1.2v -5 lead-free fpbga 484 ind 20 lfe2-20e-6fn484i 331 1.2v -6 lead-free fpbga 484 ind 20 lfe2-20e-5fn672i 402 1.2v -5 lead-free fpbga 672 ind 20 lfe2-20e-6fn672i 402 1.2v -6 lead-free fpbga 672 ind 20 part number i/os voltage grade package pins temp. luts (k) lfe2-35e-5fn484i 331 1.2v -5 lead-free fpbga 484 ind 35 lfe2-35e-6fn484i 331 1.2v -6 lead-free fpbga 484 ind 35 lfe2-35e-5fn672i 450 1.2v -5 lead-free fpbga 672 ind 35 lfe2-35e-6fn672i 450 1.2v -6 lead-free fpbga 672 ind 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50e-5fn484i 339 1.2v -5 lead-free fpbga 484 ind 50 lfe2-50e-6fn484i 339 1.2v -6 lead-free fpbga 484 ind 50 lfe2-50e-5fn672i 500 1.2v -5 lead-free fpbga 672 ind 50 lfe2-50e-6fn672i 500 1.2v -6 lead-free fpbga 672 ind 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70e-5fn672i 500 1.2v -5 lead-free fpbga 672 ind 70 lfe2-70e-6fn672i 500 1.2v -6 lead-free fpbga 672 ind 70 lfe2-70e-5fn900i 583 1.2v -5 lead-free fpbga 900 ind 70 lfe2-70e-6fn900i 583 1.2v -6 lead-free fpbga 900 ind 70
5-8 ordering information lattice semiconductor latticeecp2/m family data sheet latticeecp2 s-series devices, conventional packaging commercial part number i/os voltage grade package pins temp. luts (k) lfe2-6se-5t144c 90 1.2v -5 tqfp 144 com 6 lfe2-6se-6t144c 90 1.2v -6 tqfp 144 com 6 lfe2-6se-7t144c 90 1.2v -7 tqfp 144 com 6 lfe2-6se-5f256c 190 1.2v -5 fpbga 256 com 6 lfe2-6se-6f256c 190 1.2v -6 fpbga 256 com 6 lfe2-6se-7f256c 190 1.2v -7 fpbga 256 com 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12se-5t144c 93 1.2v -5 tqfp 144 com 12 lfe2-12se-6t144c 93 1.2v -6 tqfp 144 com 12 lfe2-12se-7t144c 93 1.2v -7 tqfp 144 com 12 lfe2-12se-5q208c 131 1.2v -5 pqfp 208 com 12 lfe2-12se-6q208c 131 1.2v -6 pqfp 208 com 12 lfe2-12se-7q208c 131 1.2v -7 pqfp 208 com 12 lfe2-12se-5f256c 193 1.2v -5 fpbga 256 com 12 lfe2-12se-6f256c 193 1.2v -6 fpbga 256 com 12 lfe2-12se-7f256c 193 1.2v -7 fpbga 256 com 12 lfe2-12se-5f484c 297 1.2v -5 fpbga 484 com 12 lfe2-12se-6f484c 297 1.2v -6 fpbga 484 com 12 lfe2-12se-7f484c 297 1.2v -7 fpbga 484 com 12 part number i/os voltage grade package pins temp. luts (k) lfe2-20se-5q208c 131 1.2v -5 pqfp 208 com 20 lfe2-20se-6q208c 131 1.2v -6 pqfp 208 com 20 lfe2-20se-7q208c 131 1.2v -7 pqfp 208 com 20 lfe2-20se-5f256c 193 1.2v -5 fpbga 256 com 20 lfe2-20se-6f256c 193 1.2v -6 fpbga 256 com 20 lfe2-20se-7f256c 193 1.2v -7 fpbga 256 com 20 lfe2-20se-5f484c 331 1.2v -5 fpbga 484 com 20 lfe2-20se-6f484c 331 1.2v -6 fpbga 484 com 20 lfe2-20se-7f484c 331 1.2v -7 fpbga 484 com 20 lfe2-20se-5f672c 402 1.2v -5 fpbga 672 com 20 lfe2-20se-6f672c 402 1.2v -6 fpbga 672 com 20 lfe2-20se-7f672c 402 1.2v -7 fpbga 672 com 20
5-9 ordering information lattice semiconductor latticeecp2/m family data sheet industrial part number i/os voltage grade package pins temp. luts (k) lfe2-35se-5f484c 331 1.2v -5 fpbga 484 com 35 lfe2-35se-6f484c 331 1.2v -6 fpbga 484 com 35 lfe2-35se-7f484c 331 1.2v -7 fpbga 484 com 35 lfe2-35se-5f672c 450 1.2v -5 fpbga 672 com 35 lfe2-35se-6f672c 450 1.2v -6 fpbga 672 com 35 lfe2-35se-7f672c 450 1.2v -7 fpbga 672 com 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50se-5f484c 339 1.2v -5 fpbga 484 com 50 lfe2-50se-6f484c 339 1.2v -6 fpbga 484 com 50 lfe2-50se-7f484c 339 1.2v -7 fpbga 484 com 50 lfe2-50se-5f672c 500 1.2v -5 fpbga 672 com 50 lfe2-50se-6f672c 500 1.2v -6 fpbga 672 com 50 lfe2-50se-7f672c 500 1.2v -7 fpbga 672 com 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70se-5f672c 500 1.2v -5 fpbga 672 com 70 lfe2-70se-6f672c 500 1.2v -6 fpbga 672 com 70 lfe2-70se-7f672c 500 1.2v -7 fpbga 672 com 70 lfe2-70se-5f900c 588 1.2v -5 fpbga 900 com 70 lfe2-70se-6f900c 588 1.2v -6 fpbga 900 com 70 lfe2-70se-7f900c 588 1.2v -7 fpbga 900 com 70 part number i/os voltage grade package pins temp. luts (k) lfe2-6se-5t144i 90 1.2v -5 tqfp 144 ind 6 lfe2-6se-6t144i 90 1.2v -6 tqfp 144 ind 6 lfe2-6se-5f256i 190 1.2v -5 fpbga 256 ind 6 lfe2-6se-6f256i 190 1.2v -6 fpbga 256 ind 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12se-5t144i 93 1.2v -5 tqfp 144 ind 12 lfe2-12se-6t144i 93 1.2v -6 tqfp 144 ind 12 lfe2-12se-5q208i 131 1.2v -5 pqfp 208 ind 12 lfe2-12se-6q208i 131 1.2v -6 pqfp 208 ind 12 lfe2-12se-5f256i 193 1.2v -5 fpbga 256 ind 12 lfe2-12se-6f256i 193 1.2v -6 fpbga 256 ind 12 lfe2-12se-5f484i 297 1.2v -5 fpbga 484 ind 12 lfe2-12se-6f484i 297 1.2v -6 fpbga 484 ind 12
5-10 ordering information lattice semiconductor latticeecp2/m family data sheet part number i/os voltage grade package pins temp. luts (k) lfe2-20se-5q208i 131 1.2v -5 pqfp 208 ind 20 lfe2-20se-6q208i 131 1.2v -6 pqfp 208 ind 20 lfe2-20se-5f256i 193 1.2v -5 fpbga 256 ind 20 lfe2-20se-6f256i 193 1.2v -6 fpbga 256 ind 20 lfe2-20se-5f484i 331 1.2v -5 fpbga 484 ind 20 lfe2-20se-6f484i 331 1.2v -6 fpbga 484 ind 20 lfe2-20se-5f672i 402 1.2v -5 fpbga 672 ind 20 lfe2-20se-6f672i 402 1.2v -6 fpbga 672 ind 20 part number i/os voltage grade package pins temp. luts (k) lfe2-35se-5f484i 331 1.2v -5 fpbga 484 ind 35 lfe2-35se-6f484i 331 1.2v -6 fpbga 484 ind 35 lfe2-35se-5f672i 450 1.2v -5 fpbga 672 ind 35 lfe2-35se-6f672i 450 1.2v -6 fpbga 672 ind 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50se-5f484i 339 1.2v -5 fpbga 484 ind 50 lfe2-50se-6f484i 339 1.2v -6 fpbga 484 ind 50 lfe2-50se-5f672i 500 1.2v -5 fpbga 672 ind 50 lfe2-50se-6f672i 500 1.2v -6 fpbga 672 ind 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70se-5f672i 500 1.2v -5 fpbga 672 ind 70 lfe2-70se-6f672i 500 1.2v -6 fpbga 672 ind 70 lfe2-70se-5f900i 588 1.2v -5 fpbga 900 ind 70 lfe2-70se-6f900i 588 1.2v -6 fpbga 900 ind 70
5-11 ordering information lattice semiconductor latticeecp2/m family data sheet latticeecp2 s-series devices, lead-free packaging commercial part number i/os voltage grade package pins temp. luts (k) lfe2-6se-5tn144c 90 1.2v -5 lead-free tqfp 144 com 6 lfe2-6se-6tn144c 90 1.2v -6 lead-free tqfp 144 com 6 lfe2-6se-7tn144c 90 1.2v -7 lead-free tqfp 144 com 6 lfe2-6se-5fn256c 190 1.2v -5 lead-free fpbga 256 com 6 lfe2-6se-6fn256c 190 1.2v -6 lead-free fpbga 256 com 6 lfe2-6se-7fn256c 190 1.2v -7 lead-free fpbga 256 com 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12se-5tn144c 93 1.2v -5 lead-free tqfp 144 com 12 lfe2-12se-6tn144c 93 1.2v -6 lead-free tqfp 144 com 12 lfe2-12se-7tn144c 93 1.2v -7 lead-free tqfp 144 com 12 lfe2-12se-5qn208c 131 1.2v -5 lead-free pqfp 208 com 12 lfe2-12se-6qn208c 131 1.2v -6 lead-free pqfp 208 com 12 lfe2-12se-7qn208c 131 1.2v -7 lead-free pqfp 208 com 12 lfe2-12se-5fn256c 193 1.2v -5 lead-free fpbga 256 com 12 lfe2-12se-6fn256c 193 1.2v -6 lead-free fpbga 256 com 12 lfe2-12se-7fn256c 193 1.2v -7 lead-free fpbga 256 com 12 lfe2-12se-5fn484c 297 1.2v -5 lead-free fpbga 484 com 12 lfe2-12se-6fn484c 297 1.2v -6 lead-free fpbga 484 com 12 lfe2-12se-7fn484c 297 1.2v -7 lead-free fpbga 484 com 12 part number i/os voltage grade package pins temp. luts (k) lfe2-20se-5qn208c 131 1.2v -5 lead-free pqfp 208 com 20 lfe2-20se-6qn208c 131 1.2v -6 lead-free pqfp 208 com 20 lfe2-20se-7qn208c 131 1.2v -7 lead-free pqfp 208 com 20 lfe2-20se-5fn256c 193 1.2v -5 lead-free fpbga 256 com 20 lfe2-20se-6fn256c 193 1.2v -6 lead-free fpbga 256 com 20 lfe2-20se-7fn256c 193 1.2v -7 lead-free fpbga 256 com 20 lfe2-20se-5fn484c 331 1.2v -5 lead-free fpbga 484 com 20 lfe2-20se-6fn484c 331 1.2v -6 lead-free fpbga 484 com 20 lfe2-20se-7fn484c 331 1.2v -7 lead-free fpbga 484 com 20 lfe2-20se-5fn672c 402 1.2v -5 lead-free fpbga 672 com 20 lfe2-20se-6fn672c 402 1.2v -6 lead-free fpbga 672 com 20 lfe2-20se-7fn672c 402 1.2v -7 lead-free fpbga 672 com 20
5-12 ordering information lattice semiconductor latticeecp2/m family data sheet industrial part number i/os voltage grade package pins temp. luts (k) lfe2-35se-5fn484c 331 1.2v -5 lead-free fpbga 484 com 35 lfe2-35se-6fn484c 331 1.2v -6 lead-free fpbga 484 com 35 lfe2-35se-7fn484c 331 1.2v -7 lead-free fpbga 484 com 35 lfe2-35se-5fn672c 450 1.2v -5 lead-free fpbga 672 com 35 lfe2-35se-6fn672c 450 1.2v -6 lead-free fpbga 672 com 35 lfe2-35se-7fn672c 450 1.2v -7 lead-free fpbga 672 com 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50se-5fn484c 339 1.2v -5 lead-free fpbga 484 com 50 lfe2-50se-6fn484c 339 1.2v -6 lead-free fpbga 484 com 50 lfe2-50se-7fn484c 339 1.2v -7 lead-free fpbga 484 com 50 lfe2-50se-5fn672c 500 1.2v -5 lead-free fpbga 672 com 50 lfe2-50se-6fn672c 500 1.2v -6 lead-free fpbga 672 com 50 lfe2-50se-7fn672c 500 1.2v -7 lead-free fpbga 672 com 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70se-5fn672c 500 1.2v -5 lead-free fpbga 672 com 70 lfe2-70se-6fn672c 500 1.2v -6 lead-free fpbga 672 com 70 lfe2-70se-7fn672c 500 1.2v -7 lead-free fpbga 672 com 70 lfe2-70se-5fn900c 588 1.2v -5 lead-free fpbga 900 com 70 lfe2-70se-6fn900c 588 1.2v -6 lead-free fpbga 900 com 70 lfe2-70se-7fn900c 588 1.2v -7 lead-free fpbga 900 com 70 part number i/os voltage grade package pins temp. luts (k) lfe2-6se-5tn144i 90 1.2v -5 lead-free tqfp 144 ind 6 lfe2-6se-6tn144i 90 1.2v -6 lead-free tqfp 144 ind 6 lfe2-6se-5fn256i 190 1.2v -5 lead-free fpbga 256 ind 6 lfe2-6se-6fn256i 190 1.2v -6 lead-free fpbga 256 ind 6 part number i/os voltage grade package pins temp. luts (k) lfe2-12se-5tn144i 93 1.2v -5 lead-free tqfp 144 ind 12 lfe2-12se-6tn144i 93 1.2v -6 lead-free tqfp 144 ind 12 lfe2-12se-5qn208i 131 1.2v -5 lead-free pqfp 208 ind 12 lfe2-12se-6qn208i 131 1.2v -6 lead-free pqfp 208 ind 12 lfe2-12se-5fn256i 193 1.2v -5 lead-free fpbga 256 ind 12 lfe2-12se-6fn256i 193 1.2v -6 lead-free fpbga 256 ind 12 lfe2-12se-5fn484i 297 1.2v -5 lead-free fpbga 484 ind 12 lfe2-12se-6fn484i 297 1.2v -6 lead-free fpbga 484 ind 12
5-13 ordering information lattice semiconductor latticeecp2/m family data sheet part number i/os voltage grade package pins temp. luts (k) lfe2-20se-5qn208i 131 1.2v -5 lead-free pqfp 208 ind 20 lfe2-20se-6qn208i 131 1.2v -6 lead-free pqfp 208 ind 20 lfe2-20se-5fn256i 193 1.2v -5 lead-free fpbga 256 ind 20 lfe2-20se-6fn256i 193 1.2v -6 lead-free fpbga 256 ind 20 lfe2-20se-5fn484i 331 1.2v -5 lead-free fpbga 484 ind 20 lfe2-20se-6fn484i 331 1.2v -6 lead-free fpbga 484 ind 20 lfe2-20se-5fn672i 402 1.2v -5 lead-free fpbga 672 ind 20 lfe2-20se-6fn672i 402 1.2v -6 lead-free fpbga 672 ind 20 part number i/os voltage grade package pins temp. luts (k) lfe2-35se-5fn484i 331 1.2v -5 lead-free fpbga 484 ind 35 lfe2-35se-6fn484i 331 1.2v -6 lead-free fpbga 484 ind 35 lfe2-35se-5fn672i 450 1.2v -5 lead-free fpbga 672 ind 35 lfe2-35se-6fn672i 450 1.2v -6 lead-free fpbga 672 ind 35 part number i/os voltage grade package pins temp. luts (k) lfe2-50se-5fn484i 339 1.2v -5 lead-free fpbga 484 ind 50 lfe2-50se-6fn484i 339 1.2v -6 lead-free fpbga 484 ind 50 lfe2-50se-5fn672i 500 1.2v -5 lead-free fpbga 672 ind 50 lfe2-50se-6fn672i 500 1.2v -6 lead-free fpbga 672 ind 50 part number i/os voltage grade package pins temp. luts (k) lfe2-70se-5fn672i 500 1.2v -5 lead-free fpbga 672 ind 70 lfe2-70se-6fn672i 500 1.2v -6 lead-free fpbga 672 ind 70 lfe2-70se-5fn900i 588 1.2v -5 lead-free fpbga 900 ind 70 lfe2-70se-6fn900i 588 1.2v -6 lead-free fpbga 900 ind 70
5-14 ordering information lattice semiconductor latticeecp2/m family data sheet latticeecp2m part number description ordering information note: latticeecp2m devices are dual marked. for example, the commercial speed grade lfe2m50e-7f672c is also marked with industrial grade -6i (lfe2m50e-6f672i). the commercial grade is one speed grade faster than the associated dual mark industrial grade. the slowest commercial grade does not have industrial markings. the markings appear as follows: lfe2m xxx xe ?x xxxxxx x grade c = commercial i = industrial logic capacity 20 = 20k luts 35 = 35k luts 50 = 50k luts 70 = 70k luts 100 = 100k luts supply voltage e = 1.2v speed 5 = slowest 6 7 = fastest package f256 = 256-ball fpbga f484 = 484-ball fpbga f672 = 672-ball fpbga f900 = 900-ball fpbga f1152 = 1152-ball fpbga f1156 = 1156-ball fpbga fn256 = 256-ball lead-free fpbga fn484 = 484-ball lead-free fpbga fn672 = 672-ball lead-free fpbga fn900 = 900-ball lead-free fpbga fn1152 = 1152-ball lead-free fpbg a fn1156 = 1156-ball lead-free fpbg a device family ecp2m (latticeecp2 fpga + serdes) encryption s = security series (encryption feature) blank = standard series (no encryption) lfe2m35e 7f672c-6i datecode lfe2m35se 7f672c-6i datecode contact your local lattice sales representative for product availability.
5-15 ordering information lattice semiconductor latticeecp2/m family data sheet latticeecp2m standard series devices, conventional packaging commercial part number i/os voltage grade package pins temp. luts (k) lfe2m20e-5f484c 304 1.2v -5 fpbga 484 com 20 lfe2m20e-6f484c 304 1.2v -6 fpbga 484 com 20 lfe2m20e-7f484c 304 1.2v -7 fpbga 484 com 20 lfe2m20e-5f256c 140 1.2v -5 fpbga 256 com 20 lfe2m20e-6f256c 140 1.2v -6 fpbga 256 com 20 lfe2m20e-7f256c 140 1.2v -7 fpbga 256 com 20 part number i/os voltage grade package pins temp. luts (k) lfe2m35e-5f672c 410 1.2v -5 fpbga 672 com 35 lfe2m35e-6f672c 410 1.2v -6 fpbga 672 com 35 lfe2m35e-7f672c 410 1.2v -7 fpbga 672 com 35 lfe2m35e-5f484c 303 1.2v -5 fpbga 484 com 35 lfe2m35e-6f484c 303 1.2v -6 fpbga 484 com 35 lfe2m35e-7f484c 303 1.2v -7 fpbga 484 com 35 lfe2m35e-5f256c 140 1.2v -5 fpbga 256 com 35 lfe2m35e-6f256c 140 1.2v -6 fpbga 256 com 35 lfe2m35e-7f256c 140 1.2v -7 fpbga 256 com 35 part number i/os voltage grade package pins temp. luts (k) lfe2m50e-5f900c 410 1.2v -5 fpbga 900 com 50 lfe2m50e-6f900c 410 1.2v -6 fpbga 900 com 50 lfe2m50e-7f900c 410 1.2v -7 fpbga 900 com 50 lfe2m50e-5f672c 372 1.2v -5 fpbga 672 com 50 lfe2m50e-6f672c 372 1.2v -6 fpbga 672 com 50 lfe2m50e-7f672c 372 1.2v -7 fpbga 672 com 50 lfe2m50e-5f484c 270 1.2v -5 fpbga 484 com 50 lfe2m50e-6f484c 270 1.2v -6 fpbga 484 com 50 lfe2m50e-7f484c 270 1.2v -7 fpbga 484 com 50 part number i/os voltage grade package pins temp. luts (k) lfe2m70e-5f1152c 430 1.2v -5 fpbga 1152 com 70 lfe2m70e-6f1152c 430 1.2v -6 fpbga 1152 com 70 lfe2m70e-7f1152c 430 1.2v -7 fpbga 1152 com 70 lfe2m70e-5f900c 416 1.2v -5 fpbga 900 com 70 lfe2m70e-6f900c 416 1.2v -6 fpbga 900 com 70 lfe2m70e-7f900c 416 1.2v -7 fpbga 900 com 70
5-16 ordering information lattice semiconductor latticeecp2/m family data sheet industrial part number i/os voltage grade package pins temp. luts (k) lfe2m100e-5f1156c 616 1.2v -5 fpbga 1156 com 100 lfe2m100e-6f1156c 616 1.2v -6 fpbga 1156 com 100 lfe2m100e-7f1156c 616 1.2v -7 fpbga 1156 com 100 lfe2m100e-5f1152c 520 1.2v -5 fpbga 1152 com 100 lfe2m100e-6f1152c 520 1.2v -6 fpbga 1152 com 100 lfe2m100e-7f1152c 520 1.2v -7 fpbga 1152 com 100 lfe2m100e-5f900c 416 1.2v -5 fpbga 900 com 100 lfe2m100e-6f900c 416 1.2v -6 fpbga 900 com 100 lfe2m100e-7f900c 416 1.2v -7 fpbga 900 com 100 part number i/os voltage grade package pins temp. luts (k) lfe2m20e-5f484i 304 1.2v -5 fpbga 484 ind 20 lfe2m20e-6f484i 304 1.2v -6 fpbga 484 ind 20 lfe2m20e-5f256i 140 1.2v -5 fpbga 256 ind 20 lfe2m20e-6f256i 140 1.2v -6 fpbga 256 ind 20 part number i/os voltage grade package pins temp. luts (k) lfe2m35e-5f672i 410 1.2v -5 fpbga 672 ind 35 lfe2m35e-6f672i 410 1.2v -6 fpbga 672 ind 35 lfe2m35e-5f484i 303 1.2v -5 fpbga 484 ind 35 lfe2m35e-6f484i 303 1.2v -6 fpbga 484 ind 35 lfe2m35e-5f256i 140 1.2v -5 fpbga 256 ind 35 lfe2m35e-6f256i 140 1.2v -6 fpbga 256 ind 35 part number i/os voltage grade package pins temp. luts (k) lfe2m50e-5f900i 410 1.2v -5 fpbga 900 ind 50 lfe2m50e-6f900i 410 1.2v -6 fpbga 900 ind 50 lfe2m50e-5f672i 372 1.2v -5 fpbga 672 ind 50 lfe2m50e-6f672i 372 1.2v -6 fpbga 672 ind 50 lfe2m50e-5f484i 270 1.2v -5 fpbga 484 ind 50 lfe2m50e-6f484i 270 1.2v -6 fpbga 484 ind 50 part number i/os voltage grade package pins temp. luts (k) lfe2m70e-5f1152i 430 1.2v -5 fpbga 1152 ind 70 lfe2m70e-6f1152i 430 1.2v -6 fpbga 1152 ind 70 lfe2m70e-5f900i 416 1.2v -5 fpbga 900 ind 70 lfe2m70e-6f900i 416 1.2v -6 fpbga 900 ind 70
5-17 ordering information lattice semiconductor latticeecp2/m family data sheet part number i/os voltage grade package pins temp. luts (k) lfe2m100e-5f1156i 616 1.2v -5 fpbga 1156 ind 100 lfe2m100e-6f1156i 616 1.2v -6 fpbga 1156 ind 100 lfe2m100e-5f1152i 520 1.2v -5 fpbga 1152 ind 100 lfe2m100e-6f1152i 520 1.2v -6 fpbga 1152 ind 100 lfe2m100e-5f900i 416 1.2v -5 fpbga 900 ind 100 lfe2m100e-6f900i 416 1.2v -6 fpbga 900 ind 100
5-18 ordering information lattice semiconductor latticeecp2/m family data sheet latticeecp2m standard series devices, lead-free packaging commercial part number i/os voltage grade package pins temp. luts (k) lfe2m20e-5fn484c 304 1.2v -5 lead-free fpbga 484 com 20 lfe2m20e-6fn484c 304 1.2v -6 lead-free fpbga 484 com 20 lfe2m20e-7fn484c 304 1.2v -7 lead-free fpbga 484 com 20 lfe2m20e-5fn256c 140 1.2v -5 lead-free fpbga 256 com 20 lfe2m20e-6fn256c 140 1.2v -6 lead-free fpbga 256 com 20 lfe2m20e-7fn256c 140 1.2v -7 lead-free fpbga 256 com 20 part number i/os voltage grade package pins temp. luts (k) lfe2m35e-5fn672c 410 1.2v -5 lead-free fpbga 672 com 35 lfe2m35e-6fn672c 410 1.2v -6 lead-free fpbga 672 com 35 lfe2m35e-7fn672c 410 1.2v -7 lead-free fpbga 672 com 35 lfe2m35e-5fn484c 303 1.2v -5 lead-free fpbga 484 com 35 lfe2m35e-6fn484c 303 1.2v -6 lead-free fpbga 484 com 35 lfe2m35e-7fn484c 303 1.2v -7 lead-free fpbga 484 com 35 lfe2m35e-5fn256c 140 1.2v -5 lead-free fpbga 256 com 35 lfe2m35e-6fn256c 140 1.2v -6 lead-free fpbga 256 com 35 lfe2m35e-7fn256c 140 1.2v -7 lead-free fpbga 256 com 35 part number i/os voltage grade package pins temp. luts (k) lfe2m50e-5fn900c 410 1.2v -5 lead-free fpbga 900 com 50 lfe2m50e-6fn900c 410 1.2v -6 lead-free fpbga 900 com 50 lfe2m50e-7fn900c 410 1.2v -7 lead-free fpbga 900 com 50 lfe2m50e-5fn672c 372 1.2v -5 lead-free fpbga 672 com 50 lfe2m50e-6fn672c 372 1.2v -6 lead-free fpbga 672 com 50 lfe2m50e-7fn672c 372 1.2v -7 lead-free fpbga 672 com 50 lfe2m50e-5fn484c 270 1.2v -5 lead-free fpbga 484 com 50 lfe2m50e-6fn484c 270 1.2v -6 lead-free fpbga 484 com 50 lfe2m50e-7fn484c 270 1.2v -7 lead-free fpbga 484 com 50 part number i/os voltage grade package pins temp. luts (k) lfe2m70e-5fn1152c 430 1.2v -5 lead-free fpbga 1152 com 70 lfe2m70e-6fn1152c 430 1.2v -6 lead-free fpbga 1152 com 70 lfe2m70e-7fn1152c 430 1.2v -7 lead-free fpbga 1152 com 70 lfe2m70e-5fn900c 416 1.2v -5 lead-free fpbga 900 com 70 lfe2m70e-6fn900c 416 1.2v -6 lead-free fpbga 900 com 70 lfe2m70e-7fn900c 416 1.2v -7 lead-free fpbga 900 com 70
5-19 ordering information lattice semiconductor latticeecp2/m family data sheet industrial part number i/os voltage grade package pins temp. luts (k) lfe2m100e-5fn1156c 616 1.2v -5 lead-free fpbga 1156 com 100 lfe2m100e-6fn1156c 616 1.2v -6 lead-free fpbga 1156 com 100 lfe2m100e-7fn1156c 616 1.2v -7 lead-free fpbga 1156 com 100 lfe2m100e-5fn1152c 520 1.2v -5 lead-free fpbga 1152 com 100 lfe2m100e-6fn1152c 520 1.2v -6 lead-free fpbga 1152 com 100 lfe2m100e-7fn1152c 520 1.2v -7 lead-free fpbga 1152 com 100 lfe2m100e-5fn900c 416 1.2v -5 lead-free fpbga 900 com 100 lfe2m100e-6fn900c 416 1.2v -6 lead-free fpbga 900 com 100 lfe2m100e-7fn900c 416 1.2v -7 lead-free fpbga 900 com 100 part number i/os voltage grade package pins temp. luts (k) lfe2m20e-5fn484i 304 1.2v -5 lead-free fpbga 484 ind 20 lfe2m20e-6fn484i 304 1.2v -6 lead-free fpbga 484 ind 20 lfe2m20e-5fn256i 140 1.2v -5 lead-free fpbga 256 ind 20 lfe2m20e-6fn256i 140 1.2v -6 lead-free fpbga 256 ind 20 part number i/os voltage grade package pins temp. luts (k) lfe2m35e-5fn672i 410 1.2v -5 lead-free fpbga 672 ind 35 lfe2m35e-6fn672i 410 1.2v -6 lead-free fpbga 672 ind 35 lfe2m35e-5fn484i 303 1.2v -5 lead-free fpbga 484 ind 35 lfe2m35e-6fn484i 303 1.2v -6 lead-free fpbga 484 ind 35 lfe2m35e-5fn256i 140 1.2v -5 lead-free fpbga 256 ind 35 lfe2m35e-6fn256i 140 1.2v -6 lead-free fpbga 256 ind 35 part number i/os voltage grade package pins temp. luts (k) lfe2m50e-5fn900i 410 1.2v -5 lead-free fpbga 900 ind 50 lfe2m50e-6fn900i 410 1.2v -6 lead-free fpbga 900 ind 50 lfe2m50e-5fn672i 372 1.2v -5 lead-free fpbga 672 ind 50 lfe2m50e-6fn672i 372 1.2v -6 lead-free fpbga 672 ind 50 lfe2m50e-5fn484i 270 1.2v -5 lead-free fpbga 484 ind 50 lfe2m50e-6fn484i 270 1.2v -6 lead-free fpbga 484 ind 50 part number i/os voltage grade package pins temp. luts (k) lfe2m70e-5fn1152i 430 1.2v -5 lead-free fpbga 1152 ind 70 lfe2m70e-6fn1152i 430 1.2v -6 lead-free fpbga 1152 ind 70 lfe2m70e-5fn900i 416 1.2v -5 lead-free fpbga 900 ind 70 lfe2m70e-6fn900i 416 1.2v -6 lead-free fpbga 900 ind 70
5-20 ordering information lattice semiconductor latticeecp2/m family data sheet latticeecp2m s-series devices, conventional packaging commercial part number i/os voltage grade package pins temp. luts (k) lfe2m100e-5fn1156i 616 1.2v -5 lead-free fpbga 1156 ind 100 lfe2m100e-6fn1156i 616 1.2v -6 lead-free fpbga 1156 ind 100 lfe2m100e-5fn1152i 520 1.2v -5 lead-free fpbga 1152 ind 100 lfe2m100e-6fn1152i 520 1.2v -6 lead-free fpbga 1152 ind 100 lfe2m100e-5fn900i 416 1.2v -5 lead-free fpbga 900 ind 100 lfe2m100e-6fn900i 416 1.2v -6 lead-free fpbga 900 ind 100 part number i/os voltage grade package pins temp. luts (k) lfe2m20se-5f484c 304 1.2v -5 fpbga 484 com 20 lfe2m20se-6f484c 304 1.2v -6 fpbga 484 com 20 lfe2m20se-7f484c 304 1.2v -7 fpbga 484 com 20 lfe2m20se-5f256c 140 1.2v -5 fpbga 256 com 20 lfe2m20se-6f256c 140 1.2v -6 fpbga 256 com 20 lfe2m20se-7f256c 140 1.2v -7 fpbga 256 com 20 part number i/os voltage grade package pins temp. luts (k) lfe2m35se-5f672c 410 1.2v -5 fpbga 672 com 35 lfe2m35se-6f672c 410 1.2v -6 fpbga 672 com 35 lfe2m35se-7f672c 410 1.2v -7 fpbga 672 com 35 lfe2m35se-5f484c 303 1.2v -5 fpbga 484 com 35 lfe2m35se-6f484c 303 1.2v -6 fpbga 484 com 35 lfe2m35se-7f484c 303 1.2v -7 fpbga 484 com 35 lfe2m35se-5f256c 140 1.2v -5 fpbga 256 com 35 lfe2m35se-6f256c 140 1.2v -6 fpbga 256 com 35 lfe2m35se-7f256c 140 1.2v -7 fpbga 256 com 35 part number i/os voltage grade package pins temp. luts (k) lfe2m50se-5f900c 410 1.2v -5 fpbga 900 com 50 lfe2m50se-6f900c 410 1.2v -6 fpbga 900 com 50 lfe2m50se-7f900c 410 1.2v -7 fpbga 900 com 50 lfe2m50se-5f672c 372 1.2v -5 fpbga 672 com 50 lfe2m50se-6f672c 372 1.2v -6 fpbga 672 com 50 lfe2m50se-7f672c 372 1.2v -7 fpbga 672 com 50 lfe2m50se-5f484c 270 1.2v -5 fpbga 484 com 50 lfe2m50se-6f484c 270 1.2v -6 fpbga 484 com 50 lfe2m50se-7f484c 270 1.2v -7 fpbga 484 com 50
5-21 ordering information lattice semiconductor latticeecp2/m family data sheet industrial part number i/os voltage grade package pins temp. luts (k) lfe2m70se-5f1152c 430 1.2v -5 fpbga 1152 com 70 lfe2m70se-6f1152c 430 1.2v -6 fpbga 1152 com 70 lfe2m70se-7f1152c 430 1.2v -7 fpbga 1152 com 70 lfe2m70se-5f900c 416 1.2v -5 fpbga 900 com 70 lfe2m70se-6f900c 416 1.2v -6 fpbga 900 com 70 lfe2m70se-7f900c 416 1.2v -7 fpbga 900 com 70 part number i/os voltage grade package pins temp. luts (k) lfe2m100se-5f1156c 616 1.2v -5 fpbga 1156 com 100 lfe2m100se-6f1156c 616 1.2v -6 fpbga 1156 com 100 lfe2m100se-7f1156c 616 1.2v -7 fpbga 1156 com 100 lfe2m100se-5f1152c 520 1.2v -5 fpbga 1152 com 100 lfe2m100se-6f1152c 520 1.2v -6 fpbga 1152 com 100 lfe2m100se-7f1152c 520 1.2v -7 fpbga 1152 com 100 lfe2m100se-5f900c 416 1.2v -5 fpbga 900 com 100 lfe2m100se-6f900c 416 1.2v -6 fpbga 900 com 100 lfe2m100se-7f900c 416 1.2v -7 fpbga 900 com 100 part number i/os voltage grade package pins temp. luts (k) lfe2m20se-5f484i 304 1.2v -5 fpbga 484 ind 20 lfe2m20se-6f484i 304 1.2v -6 fpbga 484 ind 20 lfe2m20se-5f256i 140 1.2v -5 fpbga 256 ind 20 lfe2m20se-6f256i 140 1.2v -6 fpbga 256 ind 20 part number i/os voltage grade package pins temp. luts (k) lfe2m35se-5f672i 410 1.2v -5 fpbga 672 ind 35 lfe2m35se-6f672i 410 1.2v -6 fpbga 672 ind 35 lfe2m35se-5f484i 303 1.2v -5 fpbga 484 ind 35 lfe2m35se-6f484i 303 1.2v -6 fpbga 484 ind 35 lfe2m35se-5f256i 140 1.2v -5 fpbga 256 ind 35 lfe2m35se-6f256i 140 1.2v -6 fpbga 256 ind 35 part number i/os voltage grade package pins temp. luts (k) lfe2m50se-5f900i 410 1.2v -5 fpbga 900 ind 50 lfe2m50se-6f900i 410 1.2v -6 fpbga 900 ind 50 lfe2m50se-5f672i 372 1.2v -5 fpbga 672 ind 50 lfe2m50se-6f672i 372 1.2v -6 fpbga 672 ind 50 lfe2m50se-5f484i 270 1.2v -5 fpbga 484 ind 50 lfe2m50se-6f484i 270 1.2v -6 fpbga 484 ind 50
5-22 ordering information lattice semiconductor latticeecp2/m family data sheet part number i/os voltage grade package pins temp. luts (k) lfe2m70se-5f1152i 430 1.2v -5 fpbga 1152 ind 70 lfe2m70se-6f1152i 430 1.2v -6 fpbga 1152 ind 70 lfe2m70se-5f900i 416 1.2v -5 fpbga 900 ind 70 lfe2m70se-6f900i 416 1.2v -6 fpbga 900 ind 70 part number i/os voltage grade package pins temp. luts (k) lfe2m100se-5f1156i 616 1.2v -5 fpbga 1156 ind 100 lfe2m100se-6f1156i 616 1.2v -6 fpbga 1156 ind 100 lfe2m100se-5f1152i 520 1.2v -5 fpbga 1152 ind 100 lfe2m100se-6f1152i 520 1.2v -6 fpbga 1152 ind 100 lfe2m100se-5f900i 416 1.2v -5 fpbga 900 ind 100 lfe2m100se-6f900i 416 1.2v -6 fpbga 900 ind 100
5-23 ordering information lattice semiconductor latticeecp2/m family data sheet latticeecp2m s-series devices, lead-free packaging commercial part number i/os voltage grade package pins temp. luts (k) lfe2m20se-5fn484c 304 1.2v -5 lead-free fpbga 484 com 20 lfe2m20se-6fn484c 304 1.2v -6 lead-free fpbga 484 com 20 lfe2m20se-7fn484c 304 1.2v -7 lead-free fpbga 484 com 20 lfe2m20se-5fn256c 140 1.2v -5 lead-free fpbga 256 com 20 lfe2m20se-6fn256c 140 1.2v -6 lead-free fpbga 256 com 20 lfe2m20se-7fn256c 140 1.2v -7 lead-free fpbga 256 com 20 part number i/os voltage grade package pins temp. luts (k) lfe2m35se-5fn672c 410 1.2v -5 lead-free fpbga 672 com 35 lfe2m35se-6fn672c 410 1.2v -6 lead-free fpbga 672 com 35 lfe2m35se-7fn672c 410 1.2v -7 lead-free fpbga 672 com 35 lfe2m35se-5fn484c 303 1.2v -5 lead-free fpbga 484 com 35 lfe2m35se-6fn484c 303 1.2v -6 lead-free fpbga 484 com 35 lfe2m35se-7fn484c 303 1.2v -7 lead-free fpbga 484 com 35 lfe2m35se-5fn256c 140 1.2v -5 lead-free fpbga 256 com 35 lfe2m35se-6fn256c 140 1.2v -6 lead-free fpbga 256 com 35 lfe2m35se-7fn256c 140 1.2v -7 lead-free fpbga 256 com 35 part number i/os voltage grade package pins temp. luts (k) lfe2m50se-5fn900c 410 1.2v -5 lead-free fpbga 900 com 50 lfe2m50se-6fn900c 410 1.2v -6 lead-free fpbga 900 com 50 lfe2m50se-7fn900c 410 1.2v -7 lead-free fpbga 900 com 50 lfe2m50se-5fn672c 372 1.2v -5 lead-free fpbga 672 com 50 lfe2m50se-6fn672c 372 1.2v -6 lead-free fpbga 672 com 50 lfe2m50se-7fn672c 372 1.2v -7 lead-free fpbga 672 com 50 lfe2m50se-5fn484c 270 1.2v -5 lead-free fpbga 484 com 50 lfe2m50se-6fn484c 270 1.2v -6 lead-free fpbga 484 com 50 lfe2m50se-7fn484c 270 1.2v -7 lead-free fpbga 484 com 50 part number i/os voltage grade package pins temp. luts (k) lfe2m70se-5fn1152c 430 1.2v -5 lead-free fpbga 1152 com 70 lfe2m70se-6fn1152c 430 1.2v -6 lead-free fpbga 1152 com 70 lfe2m70se-7fn1152c 430 1.2v -7 lead-free fpbga 1152 com 70 lfe2m70se-5fn900c 416 1.2v -5 lead-free fpbga 900 com 70 lfe2m70se-6fn900c 416 416 -6 lead-free fpbga 900 com 70 lfe2m70se-7fn900c 416 416 -7 lead-free fpbga 900 com 70
5-24 ordering information lattice semiconductor latticeecp2/m family data sheet industrial part number i/os voltage grade package pins temp. luts (k) lfe2m100se-5fn1156c 616 1.2v -5 lead-free fpbga 1156 com 100 lfe2m100se-6fn1156c 616 1.2v -6 lead-free fpbga 1156 com 100 lfe2m100se-7fn1156c 616 1.2v -7 lead-free fpbga 1156 com 100 lfe2m100se-5fn1152c 520 1.2v -5 lead-free fpbga 1152 com 100 lfe2m100se-6fn1152c 520 1.2v -6 lead-free fpbga 1152 com 100 lfe2m100se-7fn1152c 520 1.2v -7 lead-free fpbga 1152 com 100 lfe2m100se-5fn900c 416 1.2v -5 lead-free fpbga 900 com 100 lfe2m100se-6fn900c 416 1.2v -6 lead-free fpbga 900 com 100 lfe2m100se-7fn900c 416 1.2v -7 lead-free fpbga 900 com 100 part number i/os voltage grade package pins temp. luts (k) lfe2m20se-5fn484i 304 1.2v -5 lead-free fpbga 484 ind 20 lfe2m20se-6fn484i 304 1.2v -6 lead-free fpbga 484 ind 20 lfe2m20se-5fn256i 140 1.2v -5 lead-free fpbga 256 ind 20 lfe2m20se-6fn256i 140 1.2v -6 lead-free fpbga 256 ind 20 part number i/os voltage grade package pins temp. luts (k) lfe2m35se-5fn672i 410 1.2v -5 lead-free fpbga 672 ind 35 lfe2m35se-6fn672i 410 1.2v -6 lead-free fpbga 672 ind 35 lfe2m35se-5fn484i 303 1.2v -5 lead-free fpbga 484 ind 35 lfe2m35se-6fn484i 303 1.2v -6 lead-free fpbga 484 ind 35 lfe2m35se-5fn256i 140 1.2v -5 lead-free fpbga 256 ind 35 lfe2m35se-6fn256i 140 1.2v -6 lead-free fpbga 256 ind 35 part number i/os voltage grade package pins temp. luts (k) lfe2m50se-5fn900i 420 1.2v -5 lead-free fpbga 900 ind 50 lfe2m50se-6fn900i 420 1.2v -6 lead-free fpbga 900 ind 50 lfe2m50se-5fn672i 372 1.2v -5 lead-free fpbga 672 ind 50 lfe2m50se-6fn672i 372 1.2v -6 lead-free fpbga 672 ind 50 lfe2m50se-5fn484i 270 1.2v -5 lead-free fpbga 484 ind 50 lfe2m50se-6fn484i 270 1.2v -6 lead-free fpbga 484 ind 50 part number i/os voltage grade package pins temp. luts (k) lfe2m70se-5fn1152i 430 1.2v -5 lead-free fpbga 1152 ind 70 lfe2m70se-6fn1152i 430 1.2v -6 lead-free fpbga 1152 ind 70 lfe2m70se-5fn900i 416 1.2v -5 lead-free fpbga 900 ind 70 lfe2m70se-6fn900i 416 1.2v -6 lead-free fpbga 900 ind 70
5-25 ordering information lattice semiconductor latticeecp2/m family data sheet part number i/os voltage grade package pins temp. luts (k) lfe2m100se-5fn1156i 616 1.2v -5 lead-free fpbga 1156 ind 100 LFE2M100SE-6FN1156I 616 1.2v -6 lead-free fpbga 1156 ind 100 lfe2m100se-5fn1152i 520 1.2v -5 lead-free fpbga 1152 ind 100 lfe2m100se-6fn1152i 520 1.2v -6 lead-free fpbga 1152 ind 100 lfe2m100se-5fn900i 416 1.2v -5 lead-free fpbga 900 ind 100 lfe2m100se-6fn900i 416 1.2v -6 lead-free fpbga 900 ind 100
september 2006 advance data sheet ds1006 ?2006 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 6-1 ds1006 further info_01.0 for further information a variety of technical notes for the latticeecp2 family are available on the lattice web site at www .latticesemi.com . latticeecp2m serdes/pcs usage guide (tn1124) latticeecp2/m sysio usage guide (tn1102) latticeecp2/m sysclock pll design and usage guide (tn1103) latticeecp2/m memory usage guide (tn1104) latticeecp2/m high-speed i/o interface (tn1105) power estimation and management for latticeecp2/m devices (tn1106) latticeecp2/m sysdsp usage guide (tn1107) latticeecp2/m sysconfig usage guide (tn1108) latticeecp2/m con?uration encryption usage guide (tn1109) latticeecp2/m soft error detection (sed) usage guide (tn1113) for further information on interface standards refer to the following web sites: jedec standards (lvttl, lvcmos, sstl, hstl): www .jedec.org pci: www .pcisig.com latticeecp2/m family data sheet supplemental information
july 2007 advance data sheet ds1006 ?2007 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci?ations and information herein are subject to change without notice. www.latticesemi.com 7-1 ds1006 revision history date version section change summary february 2006 01.0 initial release. august 2006 01.1 introduction updated table 1-1 ?atticeecp2 family selection guide architecture updated ?ure 2-2 ?fu diagram updated ?ure 2-13 ?econdary clock regions ecp2-50 updated ?ure 2-25 ?ic diagram updated ?ure 2-26 ?nput register block for left, right and bottom edges updated ?ure 2-28 ?utput register block for left, right and bottom edges updated ?ure 2-30 ?qs input routing for left and right edges updated ?ure 2-32 ?dge clock, dll calibration and dqs local bus distribution table 2-15 selectable master clock (cclk) frequencies removed fre- quencies 15,20,21,22,23,30,34,41,45,51,55,60 replaced ?lkindel with ?lko updated sed section quali?d device migration capability when using dqs banks for ddr interfaces dc and switching characteristics added vccpll to the recommended operating conditions table remove note 5 from ?ot speci?ations section added note 7 & 8 to ?nitialization supply current table change note 6 - ?..down to 95mhz to ?..down to 95mhz for ddr and 133mhz for ddr2 new ?ypical building block function performance numbers new external switching characteristics numbers new internal switching characteristics numbers new family timing adders numbers updated timings for gplls, splls and dlls added syscon? waveforms. remove hstl15d_ii from sysio recommended operating condition ta b l e updated supply and initialization currents for ecp2-50 pinout information added vccpll to the signal descriptions table updated logic signal connections tables to include 484-fpbga for the ecp2-50. added logic signal connections tables for ecp2-12 devices. updated pin information summary table to include ecp2-12. updated power supply and nc connections table to include ecp2-12. added note 2 to ddr strobe (dqs) pin table added information on: pci, ddr & spi4.2 capabilities of the device- package combination latticeecp2/m family data sheet revision history
7-2 revision history lattice semiconductor latticeecp2/m family data sheet august 2006 (cont.) 01.1 (cont.) pinout information (cont.) added information on: available device resources per packaged device table ordering information updated ordering part number table to include ecp2-12. updated topside mark drawing september 2006 02.0 multiple added information regarding latticeecp2m support throughout. september 2006 02.1 dc and switching characteristics added receiver total jitter tolerance speci?ation table. removed power-up requirements for proper con?uration footnote in recommended operating conditions table. december 2006 02.2 introduction latticeecp2m selection guide table has been updated. architecture figure 2-16. per region secondary clock selection has been updated. figure 2-39. simpli?d channel block diagram for serdes and pcs has been updated. dc and switching footnotes have been added to recommended operating conditions dc electrical characteristics table has been updated. supply current (standby) tables have been updated. initialization supply current table have been updated. updated timing numbers to include lfe2-12e (rev a 0.08) pinout information updated to include the entire ecp2 device information as well as 256- fpbga and 484-fpbga pin information for the ecp2m35e. ordering information updated to include the entire ecp2 and ecp2m device ordering infor- mation. february 2007 02.3 architecture updated ebr asynchronous reset section. march 2007 02.4 dc and switching characteristics power-sequencing footnotes have been added to the recommended operating conditions. ddr2 performance has been updated to 266mhz. march 2007 02.5 introduction added ?ecurity series to the latticeecp2 and latticeecp2m families. architecture enhanced con?uration option section updated. dc and switching recommended operating conditions table - footnote 4 updated. ordering information ?ecurity series ordering part numbers added. april 2007 02.6 introduction latticeecp2m family table has been updated for user i/o counts. ordering information latticeecp2m family ordering part number section has been updated to add 1152-fpbga package for the ecp2m70 and ecp2m100. july 2007 02.7 architecture updated text in ripple mode section. dc and switching ecp2/m supply current information has been updated. typical building block function performance, external switching char- acteristics, internal switching characteristics, family timing adders, sysclock gpll timing, sysclock spll timing, dll timing and sysconfig port timing speci?ations have been updated (timing rev. a 0.10). serdes timing information has been updated. pci express timing information has been updated. pinout information added latticeecp2m20 pinout information. date version section change summary

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